Delay circuit having different high-to-low and low-to-high delays

Question

I'm trying to design an integrated circuit that can implement a delay of approximately 100 ns, working with a 180nm process. With this process, an inverter has a delay of picoseconds, so it would require too many of them in a chain to achieve such a delay. I decided to use the following circuit

It is acheiving the delay I was looking for. However, the delay is just for the low-to-high transition, in the high-to-low the delay is much lower, and I can't understand way. Here are figures of the circuit used for simulation and the results

Any explanation for the behaviour? I was expecting it to have the same delays. The inverters are ratioed Wp/Wn = 2 to achieve symmetrical propagation delays.

Answer 1

I think the problem is simply that the pulse is too short to charge the capacitor fully. I created a simulation using CD4000 series inverters at a time scale long enough that propagation delays are insignificant, and with an external resistor to ensure symmetrical output resistance. It showed the same effect as your circuit.

With this short pulse length (relative to the delay time) the capacitor barely has enough time to charge above the gate input threshold before the pulse ends, then it only has to discharge a little bit to get below the threshold again. The result is much shorter delay after the falling edge of the pulse than the leading edge.

If the pulse was longer or the on/off ratio was closer to 50% the delays would be more symmetrical, but if you need to delay a short intermittent pulse while maintaining its width this technique is not suitable.