I sometimes make mistake when changing VHDL code to add new functionality that, the new signals added into the VHDL process are not reset when the reset state is asserted. This mistake could be quite harmless sometimes but at other times it can lead to design failure in simulation or even hardware.
What tool do I use to ensure that all signals and variables used inside a process are assigned an initial value in the process, maybe when reset is asserted or maybe every clock cycle?
There are industry-standard formal verification tools like QuestaSim Autocheck which can be used for variety of static and dynamic checks on various aspects of RTL design at the earlier stages of development, without the need of a simulation test bench.
Reset values of registers is one of the many checks supported by the tool.
What tool do I use to ensure that all signals and variables used inside a process are assigned an initial value in the process, maybe when reset is asserted or maybe every clock cycle?
Same as every other test: you write a testbench that checks for defined value.
I don't have any tool to suggest but possible check by simulation.
I do a visual inspection on simulation waveforms at unit testing. Before asserting the reset, they are all undefined (easy to see - in red). After the reset asserted, they are initialized (see them in green). When one is not reset by mistake it is quickly found scrolling all signals.
That works well for my designs in which the coding rule is to reset all signals (even if not always recommended).
