Multi-input NAND gate or Multiple 2-input NAND gates (VLSI design)

Question

I am unsure which option is best practice from those featured in the title. This is part of some VLSI coursework I am doing in Cadence and so will need to do the layout of this design as well.

For example, if I have 5 inputs and I only want a high output when each is high - is it best to create a 5-input NAND gate (from 5 PMOS and 5 NMOS transistors) or link together 3 2-input NAND gates?

Logically, the 5-input NAND gate uses fewer transistores but will result in wider pMOSFET channels

Thanks in advance

Answer 1

This depends on the process and area vs. speed trade-offs. Clearly, making a NAND5 using 5 p-FETs and 5 n-FETs would be the simplest in theory, but it might not be the most effective. For one thing, the pull-down network resistance begins to get large, which would slow down the fall time if a large capacitance is being driven.

Synthesis will instead probably realize a NAND5 as multiple gates using standard cells, rather than using the fewest-transistors solution. As it is, typical libraries don't have bigger fan-ins than 4.

Example: http://www.vlsitechnology.org/html/cells/wsclib013/lib_gif_index.html

Another: https://www.cl.cam.ac.uk/teaching/0910/SysOnChip/tanner_ami.pdf