my DAC FS is 18V while ADC FS is 2.5V thus the FPGA has to divide the
value by ~7.2 to map ADC FS to DAC correct?
Well, you could do it that way but you'd be losing resolution so, why not just do an analogue potential divider "divide" on the output of your DAC to convert a full scale of 18 volts to a full scale of 2.5 volts.
Most DACs are used to transmit an analogue signal to something that uses that analogue signal and so adding two resistors to the DAC interface circuit seems trivial so, how would you divide by 7.2: -
simulate this circuit – Schematic created using CircuitLab
Regarding your original question, If you handled the top 16 bits (the most significant ones) with a DAC having a reference of 18 volts and you handled the lower 8 bits with a DAC having a reference of 18 volts divided by 65536 (i.e. 0.27466 mV) you could then imagine an analogue adder on the output would perfectly produce a full 24 bit waveform.
But, if you didn't bother with the 8 bit DAC then you are only "losing" resolution in the order of a quarter of a millivolt. Does this make sense as to what is happening by ignoring the lower 8 bits?