Determining how much load capacitance a 40-series logic IC can safely drive

Question

In designing a circuit, meant to delay only the rising edge of a square wave, I've got some doubts on determining the maximum value for C1 that can safely be driven by the CD40106 CMOS logic IC.

The discharging part of the cycle is no problem as that happens trough R1, but the charging is done directly trough D1 for as little delay as possible. I can't find any hard current-limits, maximum load capacitance or similar numbers in the datasheet.

How I think it's done:

The datasheet lists some maximum power dissipation numbers for the whole device and per output-transistor, along with the available output current for a given output voltage and VCC:

So, a worst-case number of -2.4 mA @ 13.5V out for a 15 VCC implies a output resistance of:

$$\frac{15 V - 13.5V}{2.4mA} = 625 \Omega$$

One can then calculate the average power dissipated in 625 Ohm for a given C1 value and switching frequency and see if it does not exceed the maximum power dissipation numbers.

Is this method correct? Please detail the correct method if not.

Answer 1

CMOS 4000-series logic operating from 3-5V can sustain outputs continuously shorted to either supply rail. So capacitors don't really matter - they are just "poor" shorts.

You don't need to use 15V VCC for RC circuitry, since it's meant to be slow, so you can drive the RC circuit from 3-5V, and use the output driver schmitt gate to drive an open-collector stage to step the voltage up to 15V:

^{simulate this circuit – Schematic created using CircuitLab}

Answer 2

The output model envisioned is a rather simple linear one. The PMOS pull-up transistor has a voltage-current characteristic that is far less linear.
Pegging output resistance to one value is a less-than-accurate approach. Some insight to variations in equivalent output resistance might be gleaned from Texas Instrument CD40106B data sheet:

Answer 3

Rather than try to calculate and integrate I*V, you can consider that all the ½.C.V^2 energy required to charge the capacitor (ignoring the diode drops) comes from the output via the supply. Therefore the energy dissipated to charge the capacitor is also ½.C.V^2. Therefore you power is ½.C.V^2.f

CMOS ICs are no intended to operate at maximum power dissipation continuously, and there can't be a real guarantee of long term (years) reliability under this condition.

A better approach is to make U1B an OR-type gate; delete the diode, and drive the other input of the OR directly from U1A. Thus as U1A's output rises, the OR's output will rise immediately (even faster than your circuit); conversely when U1A falls, it will require the R.C to discharge and thus generate a delay.

This also has the advantage of dissipating most of the power in the resistor which can handle it reliably.

Instead of a Schmitt trigger, you can use a normal buffer (OR gate, not NOR gate), and add a small (say 10 % of C1) capacitor between input and output. This creates positive feedback with similar performance to a Schmitt trigger.

Answer 4

If I was really trying to charge that cap as quickly as possible, I would probably consider spending a couple of cents on an output drive transistor, to make things a bit more predictable and almost certainly faster.

However your phrase "as little delay as possible" leaves me with a feeling of incompleteness. There must be some minimum (1ns? 10ns? 100ns?) which is definitely tolerable and I would begin by trying to define that, otherwise it's rather hard to decide what is or is not a good solution.

With this kind of situation it also becomes important to know a bit more about your design objectives. Are you making one or ten thousand of these? (This would make me think about how much I trust those graphs of output characteristic to be reliably true for every chip in a big batch.) Is cost of extra parts a big deal (i.e. are you trying to shave every last cent off the cost?)

As I consider this circuit, I realise that there are two parameters at play here - the DELAY through the circuit (which you want to minimise) and the required PULSE WIDTH at the input to charge C fully and thus ensure that the delay is achieved. (A short pulse will cause incomplete charge and thus possibly a reduced delay.)

You could add one resistor and limit the charge current into C, while still having the output respond to the input with minimum delay. I think this helps your delay figures (as you now know the output voltage of the first stage will not be stuck low for a short period trying to charge the cap), at the expense of a longer (but well defined) input pulse to charge the cap fully. There is some dependence between pulse width and delay here, you may need to think about that (but there was before as well for very short pulses).

The values given here are notional, R1 sets the delay and R2 sets the minimum pulse width of the input that will cause the delay to take effect. For the values I give, the minimum pulse is around 20uS and the delay is about 0.5s (very approximate), of course you can adjust these to fit your application.

^{simulate this circuit – Schematic created using CircuitLab}