Consider the attached discussion of a reduced MIPS microprocessor from Weste and Harris's CMOS VLSI Design. My recollection of my computer organization course is relatively weak, so I'm hoping someone can clarify two quick questions I had:
(1) Why doesn't \$Destination\$ need to be multiplied by 4 as with \$Imm\$ in the BEQ instruction, and as per footnote a?
(2) If the PC has 8 bits, how is that we can put \$Destination\$ (with 26 bits) in it?
(1) In MIPS assembly, when dealing with the BEQ instruction, the Imm represents the offset in words, not bytes. Since MIPS instructions are 32 bits or 4 bytes long, the offset is specified in words, and it is implicitly multiplied by 4 during instruction execution. This is why the Imm is multiplied by 4.
However, for the Destination in the BEQ instruction, it refers to the target address to which the PC jumps if the branch condition is true. The Destination in this context represents the actual address, not an offset, so it doesn't need to be multiplied by 4.
(2) In MIPS Assembly, the Destination field in the BEQ instruction is a 26-bit field. The full 26 bits of the Destination are not directly placed into the PC. Instead, the branch target address is calculated by concatenating the upper 4 bits of the PC with the 26-bit Destination, effectively providing a 32-bit target address. This ensures that the branch target address fits within the available address space.
