Why are drain and source not actually perfectly symmetric?

Question

In textbook treatments, one has that the source and drain of a MOSFET are completely symmetrical and therefore interchangeable -- the distinction is only made by which is at a higher voltage in the circuit in which the MOSFET is used. Gray and Meyer (Analysis and Design of Analog Integrated Circuits, 5e) however note that "In practice, the symmetry is good but not perfect."

Why is the symmetry not perfect? Is it the case that fab processes actually design drain and source diffusions slightly differently (for, say, the unit transistor in a given process) or is the "in practice" caveat simply to note that drains will be connected to, for example, an output node with lots of other connections thereto whereas a source might not be. That is, is the "in practice" distinction between source and drain intrinsic to the process or simply about how we electrically connect them in most circuit designs?

Answer 1

Generally, transistors used in logic circuits do have symmetrical source and drain characteristics. This includes the basic design and layout of the device, halo doping effects, VT adjusts and strain effects.

Devices used for analog circuits may, and all high voltage devices have asymmetrical source and drain structures. This is because the source will not be biased more than a small voltage (say < 5 V) above the bulk, and VGS will not exceed a similar small value. However the drain may need to withstand very high voltages (to 1000 V) -- therefore it needs a lighter doping than the source (and portions of it need to be spaced further aways from the gate structure).

For HV devices, this has the effect of adding a significant resistance in series with the drain (which is not present in the source side). This alone gives a different DC characteristic to the device. The additional capacitance associated with the drain gives a different AC characteristic.

Answer 2

After doing some reading, it seems we can make the following observations which answer the question:

1. There are differences associated with the channel at either end of the MOSFET.

Strain: This technique involves altering the crystal lattice structure of the silicon in the channel region to improve carrier mobility. The application of strain can be different near the source and drain regions, leading to asymmetrical electrical characteristics. For instance, tensile strain might be applied near the drain to enhance electron mobility in nMOS devices, which can make the drain region's electrical properties slightly different from the source. Incidentally, there are various reasons you might introduce more strain at the drain end than at the source end, but whatever these reasons they lead to a difference between the source and drain.

Halo Doping: Halo or pocket doping involves implanting impurities in the substrate around the source and drain regions to control short channel effects like threshold voltage roll-off and punch-through. The concentration and distribution of these dopants can differ between the source and drain, leading to asymmetries. For example, heavier doping near the drain side can be used to manage hot carrier effects, which introduces a difference between the source and drain.

2. There is another category of differences associated with geometry and layout of the diffusions.

Physical Dimensions: The actual physical dimensions of the source and drain regions can be intentionally varied. For example, in some power MOSFET designs, the drain region is made larger to handle the higher voltage drop, while the source is optimized for better on-state resistance.

Parasitic Elements: The layout of the MOSFET on the chip can lead to different parasitic capacitances and resistances at the source and drain. For example, if the drain is located farther from the gate than the source due to layout constraints, this can lead to higher drain-gate capacitance. (This point was referenced in my question but it is not really intrinsic to device operation. That is, if we "flipped" the device around in an otherwise symmetrical textbook MOSFET we would get the same operation.)