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Clock crossing FIFOs are essential components of multiple clock designs. I wish to understand, must they be built from Block RAM (i.e hard memory blocks) or they can also be built using registers?

The reason I am asking is quite simple. A single BRAM has quite a lot of space inside it. If we need a Clock Crossing FIFO that is not deep and needs only a few bytes at most, we would end up wasting most of the BRAM space. In this case, it makes sense to use the logic resource of the design.

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  • \$\begingroup\$ LUTRAM can also be used for smaller FIFOs. \$\endgroup\$
    – Dave Tweed
    Commented Aug 6 at 22:47
  • \$\begingroup\$ I like the ZipCPU site for educating myself on FPGA coding. There's this link on Crossing clock domains with an Asynchronous FIFO and this link on Minimizing FPGA Resource Utilization, which has a section on using block RAM. I'm only suggesting them as worthy of a good read that may help. Not as a solution to your question (or I would have added an answer and referred to those pages.) \$\endgroup\$
    – periblepsis
    Commented Aug 6 at 23:44
  • \$\begingroup\$ I never knew about something called LUTRAM. I assume that this is something Xilinx specific? \$\endgroup\$
    – gyuunyuu
    Commented Aug 7 at 10:49
  • \$\begingroup\$ I think so. LUTs are RAM, so Xilinx made it easy to use them as application-level RAM. \$\endgroup\$
    – Dave Tweed
    Commented Aug 7 at 12:15
  • \$\begingroup\$ @gyuunyuu The LUTRAM as a feature is not specific to Xilinx. Another name for it is distributed ram, many FPGA vendors provide it, though not in all series of FPGA. \$\endgroup\$
    – Vlad
    Commented Aug 7 at 12:22

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