Questions tagged [cdc]
Clock Domain Crossing. Used where information is transferred from synchronous logic from one clock source to synchronous logic using a different clock source.
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USB CDC device send response of first for second data
I'm working using atmel studio 7.0, the code which i'm using is USB Communication Device Class (CDC) for ATSAMD21. My application is to read the command from the host to the device and perform the ...
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3answers
110 views
Multiple Reset Synchronization
I have two active low async resets (rst_na and rst_nb) and associated two clocks (clk_a and clk_b). Assume Block B required ...
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0answers
29 views
Multicycle path formulation
What is the significance of "multicycle path formulation" in Clock domain crossing? How can one come to know whether to use Multi path cycle formulation or not?
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2answers
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Clock Domain Crossing
While reading the concept of CLOCK DOMAIN CROSSING I came across the 2 flip-flop synchronizer. If my first flop goes into metastable state, then how will it detect the correct value of data when it ...
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1answer
25 views
SDC constraints for source clock and derived clock
There are two clocks in the system, clk2 is derived from clk1 with a 180-degree phase shift. There is 1bit data from clk1 to clk2.
I know this is a kind of asynchronous scenario and the traditional ...
2
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3answers
60 views
Clock domain cross and metastablilty problem
I understand the problem of metastability and understand that we can't get a stable value in a bounded time so we need unbonded time but it is not practical,
so we put another flip flop with no ...
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1answer
307 views
Testing STM32 USB CDC TX and RX with 2 Linux terminals
I programmed a simple USB CDC (virtual COM port) communication on a STM32L476RG with STM32CubeMX and HAL : when the MCU receives the command "LDRT", it toggles a red LED on the board, and sends its ...
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2answers
129 views
Temperature and Voltage variation affects on Metastability
Are there any effects of temperature and voltage variations on Metastability of the flip-flop? If Yes, What are the effects?
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2answers
173 views
Crossing independent domain clocks (slow to fast)
I have 2 time domain clocks (completely independent) and a bit stream (single bit)
The first clocks is at 12.29 MHz .
I want to asynchronously reclock it to a second time domain.
Meta stability is ...
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1answer
1k views
stm32 CDC USB - Unknown device (error code 43) [closed]
I face a problem with making custom PCB with STM32F103C8T6 FS CDC but whole story looked like this.
I've made small test app using CubeMX and IAR on cheap PC from china with same MCU - in terminal on ...
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1answer
810 views
Asynchronous FIFO cdc question
1) Why there is no multi-bit synchronization problem for slow clock domain ? it is obvious that the pointers could increment by more than one.
Screenshot from sunburst asynchronous FIFO paper page 12
...
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1answer
2k views
STM32F7 discovery USB device CDC using CubeMX
The thing I want to do is sending some bytes with STM32F7 discovery to my laptop, through USB (HS or FS). I tested the virtual com example provided by keil microvision so the hardware is OK, but I ...
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76 views
How is interaction with CDC device with no interface endpoints working?
I'm working on uploading to Digispark board. It uses micronucleus bootloader and i can see uploader code. I've modified it a bit to see interfaces and endpoints count:
...
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2answers
201 views
What usb-class for a device intended to be as future proof as possible?
I am writing specifications for a product and need help to minimize its future need of maintenance.
In order to be able to be (optionally) monitored from the Internet the device is supposed to have a ...
3
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3answers
195 views
Can I use 2 Flop synchronizer to migrate a pulse from one clock domain to another provided that clocks phase shifted but of same frequency?
I want to migrate this signal from CLKA to CLKB. Frequencies of both the clocks are same but they are out of phase.
Can 2-Flop synchronizer be used for this? Please note that the signal can be low/...
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1answer
479 views
Asynchronous FIFO for fast-write-slow-read
I'm not quite sure how to generate full signal in a FIFO with fast-write and slow-read. Eg., if f_wr=10*f_rd, when the updated writing pointer is synchronized to reading side using simple ...
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3answers
1k views
USB on STM32F107RCT and Stm32CubeMX
I have STM32f107 MCU soldered on custom board. I would like to use USB peripheral in CDC mode. I connected pins PA11 (D-), PA12 (D+) and GND directly to a USB cable which leads to the computer. The ...
2
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1answer
162 views
Distinguishing clock domains in designs
I am finding it confusing in defining various clock domains in the design. I did search over the Internet but I didn’t get a complete clarity on this.
In a certain FPGA (Actel ProASIC series) based ...
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1answer
692 views
STM32F4 USB CDC Communication transfers only specific characters without noise?
I'm working with STM32F407VET6 board. And I'm trying to make communication between my PC and Micro Controller via sample which transmits what it receives through USB. I've created USB Device example ...
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2answers
1k views
Clock Domain Crossing for Pulse and Level Signal
For pulse we use Pulse-Synchronizer and for Level Signal we use 2-flop synchronizer but what if the signal can be of Pulse or Level behaviour. Is there any way to synchronize that?
EDIT:
After @...
9
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2answers
5k views
How does 2-ff synchronizer ensure proper synchonization?
Using 2-ff synchronizers has been a standard for a signal to cross clock boundaries. And there are lots of paper/figures illustrating the mechanism, such as this one:
It seems bclk can only sample ...
4
votes
2answers
591 views
Metastability error propagation with flip flop
I do have a confusion regarding the metastability resolution using flip flops , I know that I should add synchronizer of two or three d-flip flop to guarantee a safe transmission at clock domain ...
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1answer
196 views
What will the output of filp-flop if its input is metastable?
I was reading sunburst paper on Clock Domain Crossing and got stuck with this doubt.
Here in the 3rd flip flop, input is metastable state but at the rising edge of the clock output was set to high. ...
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2answers
1k views
SDC constraints for two flop sychronizer
I have doubt, What should be proper SDC constraint for CDC module, i.e., two flop synchronizer.
between "dat driving by aclk to <...
4
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1answer
2k views
CDC Synchonisation primitives for an Altera FPGA
I am working on my first non-trival FPGA design and finally have a need for Clock Domain Crossing (CDC).
There are multiple resources (amongst others) which discuss various architectures for CDC and ...
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2answers
2k views
Clock domain crossing timing constraints for Altera
I have a slight problem with my clock domain crossing timing constraints.
I have two clock groups
set_clock_groups -asynchronous -group {clk_A} -group {clk_B}
...
3
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2answers
1k views
cross clock domain databus
I asked a question some time ago about crossing clock domains
Design practice crossing clock domains and async signals.
One of the "rules" is to never synchronize multi-bit signal bit-by-bit, ...
4
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3answers
5k views
Design practice crossing clock domains and async signals
I have been designing a few projects on different FPGA's in VHDL, and it seems my most common source of "hard to find errors" is when I forget to synchronize an async signal, or forgets to resync a ...
