Questions tagged [cdc]

Clock Domain Crossing. Used where information is transferred from synchronous logic from one clock source to synchronous logic using a different clock source.

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How to properly implement an n-FF synchronizer in Lattice FPGAs?

Unlike Xilinx which provides their users with a set of convenient xpm_cdc_* modules, Lattice does not seem to have “the standard” way for clock domain crossing. So ...
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When is it safe to ignore clock-domain crossing results from Microchip (Microsemi) Libero SoC's CDC report?

Inside my design, I'm only adding synchronizers to the control signals traveling between two different clock domains. The data buses are aligned with a pretty simple handshake scheme and don't have ...
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How to calculate the number of required flip-flop stages needed for clock-domain crossing?

In a given scenario where I have two clock domains driven by a 200MHz and a 30 MHz external independent clocks, what would be the best way to calculate the number of flip-flop stages needed for proper ...
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What's the criterion to move from only having CDC for the control lines to include the data buses?

I've noticed that in most designs synchronized signals crossing clock domains are implemented for control signals. I'm, however, wondering what the criteria is to add synchronization to the data bus ...
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does a 2-flip-flop synchronizer for clock domain crossing need a clear (reset) input signal?

In my current FPGA design, I have a fast clock that has to travel to multiple locations inside the device. Among those locations, I have a set of 2-flip-flop synchronizers for clock-domain crossing ...
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Why 1.5x ratio limitation for synchronizing slow signals into fast clock domain?

Why 1.5x ratio limitation for Synchronizing Slow Signals Into Fast Clock Domain ?
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What is the difference between "2 synchronize" and "metastability"?

As far as I know, 2 synchronize used to be used in in asynchronous FIFO for preventing metastability in multi clock domain. as the below, cross clock domain databus But I came across about ...
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Metastability in 3 or 2 flop synchronizer if input is valid for at least 2 clocks

In this image: Figure 1: metastability in 2 or 3 flop synchronizer If the metastability of first flop doesn't get resolved in 4th clock, is it possible that it may get resolved to '0' in 5th clock? ...
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Is metastability not a concern in CDC if the signal in source clock is at least 3x wide as that of destination clock's period?

There are so much hype and concern over metastability in cross clock domain. If the goal as an ASIC/FPGA designer is to ensure that the signal in source clock get propagated to destination clock even ...
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How do I know when I have to use clock domain crossing? [closed]

What is the reason behind clock domain crossing? When do I use it? Do I use it only when I am transferring data from one CLK to another?
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How to track down all the registers connected to a specific downstream register? (for set_max_delay's --from)

The Xilinx Vivado's set_max_delay requires -from to be set. Basically I'd like to set max delay TO a register. Because there can ...
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Asynchronous FIFO design with PULSE synchronizer

I'm trying to understand various implementations of asynchronous FIFO from the following link https://inst.eecs.berkeley.edu/~cs150/sp10/Collections/Discussion/Honors/Honors14_1PP.pdf In the slide 7 ...
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Why do we use a gray encoded signal by 2 stage flip-flop in asynchronous FIFO to avoid race-condition issue? [duplicate]

In the FIFO design, to compare the rptr and wptr, we are feeding one signal into another clock domain. The rptr which is coming from the slow clock domain to faster one can be synchronized with sync ...
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what is the specific reason for using FIFO in asynchronous domain at VLSI?

I was wondering that the reason of using FIFO in asynchronous domain at VLSI. Basically, to prevent x propagation in asynchronous domain(aka CDC domain), I was taken care of 2 stage F/F method for ...
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questions about up-sampling and moving from slow to fast clock domain in FPGA

I encountered some questions and problems I asked myself lately and hoped I can get a nice lead here before I start reading long articles without even be sure if it's the right way. Let's assume I ...
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Clock domain crossing between OV7670 interface and AXI4-Stream

Update 1: My first approach is to use the xpm_cdc_handshake macro in the following way: ...
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Maximum data rate that can be achieved between PIC and FPGA

We are looking at PIC24FJ256GA705 here. It is connected to an FPGA and the FPGA must transfer a few kB of data as fast as possible. I assume that parallel transfer is the best option here, parallel ...
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SDC Constraints for digitally noise filtered CLOCK and DATA inputs

I need help if my SDC constraints are correct for a digitally noise filtered CLOCK and DATA inputs. I'm not sure if CLK3 grouping and create_clk CLK2 are correct. I would like to know on how to make a ...
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Handling of reset with multi bit clock domain crossing

I have an SoC design with two clock domains, each with it's own asynchronous reset (which roughly means asynchronous assertion of reset and synchronous de-assertion). I am trying to pass a 64 bit ...
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Syntax and/or best practice for buffering a vector in Verilog or VHDL

I have a Verilog block (Block A) that samples a serial signal with a relatively slow clock and then puts data in several registers based on the contents of the serial data. Ultimately, these data ...
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Clock Dividers with Clock Domain Crossing

I am doing a design in FPGA that looks like this: 100 MHz is the clock available in my FPGA board. It feeds Module 2. Module 1 is needs a slow clock of 10 MHz clock. So I used a clock divider with ...
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Why double synchronizer alone is not enough for multi byte transfer between two clock domains?

When one bit information is transferred between two different clock domains, we use 2 Flip-flops or double synchronizers. But when we transfer multi bit signals across two different clock domains, why ...
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gray code clock domain crossing FIFO fast to slow

I'm trying to understand how clock crossing FIFOs are implemented, and the usual answer I see to convert the read/write address pointers to gray code and then pass through synchronizer circuits into ...
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3 answers
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Multiple Reset Synchronization

I have two active low async resets (rst_na and rst_nb) and associated two clocks (clk_a and clk_b). Assume Block B required ...
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Clock Domain Crossing

While reading the concept of CLOCK DOMAIN CROSSING I came across the 2 flip-flop synchronizer. If my first flop goes into metastable state, then how will it detect the correct value of data when it ...
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SDC constraints for source clock and derived clock

There are two clocks in the system, clk2 is derived from clk1 with a 180-degree phase shift. There is 1-bit data from clk1 to clk2. I know this is a kind of asynchronous scenario and the traditional ...
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Clock domain cross and metastablilty problem

I understand the problem of metastability and understand that we can't get a stable value in a bounded time so we need unbonded time but it is not practical, so we put another flip flop with no ...
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Temperature and Voltage variation affects on Metastability

Are there any effects of temperature and voltage variations on Metastability of the flip-flop? If Yes, What are the effects?
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Crossing independent domain clocks (slow to fast)

I have 2 time domain clocks (completely independent) and a bit stream (single bit) The first clocks is at 12.29 MHz . I want to asynchronously reclock it to a second time domain. Meta stability is ...
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possible clock domain crossing?

Please see the following code. (For the sake of clarity, it is a YCbCr 4:2:2 to 4:4:4 SerDes.) ...
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Asynchronous FIFO cdc question

1) Why there is no multi-bit synchronization problem for slow clock domain ? it is obvious that the pointers could increment by more than one. Screenshot from sunburst asynchronous FIFO paper page 12 ...
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Can I use 2 Flop synchronizer to migrate a pulse from one clock domain to another provided that clocks phase shifted but of same frequency?

I want to migrate this signal from CLKA to CLKB. Frequencies of both the clocks are same but they are out of phase. Can 2-Flop synchronizer be used for this? Please note that the signal can be low/...
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Asynchronous FIFO for fast-write-slow-read

I'm not quite sure how to generate full signal in a FIFO with fast-write and slow-read. Eg., if f_wr=10*f_rd, when the updated writing pointer is synchronized to reading side using simple ...
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Distinguishing clock domains in designs

I am finding it confusing in defining various clock domains in the design. I did search over the Internet but I didn’t get a complete clarity on this. In a certain FPGA (Actel ProASIC series) based ...
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Clock Domain Crossing for Pulse and Level Signal

For pulse we use Pulse-Synchronizer and for Level Signal we use 2-flop synchronizer but what if the signal can be of Pulse or Level behaviour. Is there any way to synchronize that? EDIT: After @...
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11 votes
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How does 2-ff synchronizer ensure proper synchonization?

Using 2-ff synchronizers has been a standard for a signal to cross clock boundaries. And there are lots of paper/figures illustrating the mechanism, such as this one: It seems bclk can only sample ...
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Metastability error propagation with flip flop

I do have a confusion regarding the metastability resolution using flip flops , I know that I should add synchronizer of two or three d-flip flop to guarantee a safe transmission at clock domain ...
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What will the output of filp-flop if its input is metastable?

I was reading sunburst paper on Clock Domain Crossing and got stuck with this doubt. Here in the 3rd flip flop, input is metastable state but at the rising edge of the clock output was set to high. ...
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SDC constraints for two flop sychronizer

I have doubt, What should be proper SDC constraint for CDC module, i.e., two flop synchronizer. between "dat driving by aclk to <...
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CDC Synchonisation primitives for an Altera FPGA

I am working on my first non-trival FPGA design and finally have a need for Clock Domain Crossing (CDC). There are multiple resources (amongst others) which discuss various architectures for CDC and ...
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Clock domain crossing timing constraints for Altera

I have a slight problem with my clock domain crossing timing constraints. I have two clock groups set_clock_groups -asynchronous -group {clk_A} -group {clk_B} ...
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cross clock domain databus

I asked a question some time ago about crossing clock domains Design practice crossing clock domains and async signals. One of the "rules" is to never synchronize multi-bit signal bit-by-bit, ...
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Design practice crossing clock domains and async signals

I have been designing a few projects on different FPGA's in VHDL, and it seems my most common source of "hard to find errors" is when I forget to synchronize an async signal, or forgets to resync a ...
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