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Well this is a continuation of my question on FPGA over here.

I finally selected a Digilent Atlys with a Spartan 6 FPGA, I don't have any prior experience of FPGA's although I have done some amount of work with micro-controllers.

I spent the last few days reading through data sheets of the FPGA, and I think it would be a good choice to start off with Verilog. I couldn't find any code examples though and even the data sheets are not newbie friendly.

I want to do some hand's on programming, simulation, synthesis now and this is what I want to do

  1. Generate an odd frequency, say 54Mhz from the FPGA (it runs on a 100Mhz clock) and route it to one of the pins. I would probably have to use the DCM or PLL for this, but no idea how to start here?

  2. Implement some sort of I2C read write from the FPGA.

What I'm looking for is a reference, possibly an online one or a book that gives me code examples and description of each of the hardware components available inside the FPGA, like DCM's, slices, clb's etc.

I guess that should get me started into the world of FPGA's.

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Code Examples

Hop over to OpenCores and you will find dozens of open source projects. There are many written in Verilog and cover the gamut from I/O devices through to processors.

Also, do not forget the many Application Notes available from Xilinx. They are very helpful with their own devices.

Design Flow

Pick up a book or two on design flow so that you get an overview on the steps involved in FPGA design. In summary, they will involve:

  1. Design entry - in your case, Verilog.
  2. Functional simulation - using various tools.
  3. Synthesis - in your case, using the Xilinx ISE tools.
  4. Simulation - to verify your post-synthesis design because some aspects of Verilog are not synthesisable.
  5. Place & Route - using the Xilinx ISE tools.
  6. Implementation - downloading the design onto the FPGA.
  7. Testing.

FPGA Components

As for using the FPGA components, there are different ways to use them. But assuming that you are using a Verilog design entry, you can either infer or instantiate the different components.

Inference generally involves getting the synthesis tool to pick the best components to use based on the functionality that you require. The best example of this would be to design an adder.

By doing q <= a + b or q = a + b you can infer an adder. Both will infer the adder but there is a difference in when you use the blocking/non-blocking syntax.

Instantiation generally involves calling the exact library component in code. Some components just cannot be easily inferred in code - such as the DCM. You can use the ISE tools and examples to learn more about this.

The actual list of components themselves are provided by Xilinx in the Libraries Guide.

Protip

The best way to learn this is actually to experiment with short bits of code and run them through the ISE synthesis to see what it spits out. There are also plenty of examples in the ISE toolset itself.

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Your absolute references will be the Spartan 6 user guides. For instance, the Clocking Resources guide (UG382) covers how to configure the DCMs. For examples of how the actual code looks, ISE has a database of them. Open Language Templates (the lightbulb in the toolbar), then look in language (VHDL or Verilog) -> Device Primitive Instantiation -> chip family (Spartan-6) -> Clock Components.

Details specific to your board are available from Digilent, in particular you'll want the UCF (which names all the IOs) and the reference manual (which explains the peripheral circuitry).

The general structure of your language, including how to make a component, is probably better picked up from books and examples. I haven't used Verilog so don't have any specific suggestions. Still, the templates include snippets of various generic contructs as well.

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  • \$\begingroup\$ Do you specialize in VHDL? Regarding the UCF why would it be important for working with the Digilent board? \$\endgroup\$ – Kevin Boyd Jan 12 '11 at 13:55
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    \$\begingroup\$ I don't specialize as such - just haven̈́'t studied Verilog. The UCF is the file that describes which pins your ports connect to, as well as clocking demands. Without it, pins are assigned randomly, which won't match the existing board. \$\endgroup\$ – Yann Vernier Jan 12 '11 at 20:15
  • \$\begingroup\$ I understood the pin assignment part what's about the clocking demands? \$\endgroup\$ – Kevin Boyd Jan 14 '11 at 5:03
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    \$\begingroup\$ Timing constraints cover things like clock frequency, setup and hold times. You'll still get the information in the timing analysis, but specifying the requirements in the constraints file lets the tools detect when they fail, and possibly try harder to satisfy your needs when it's borderline. \$\endgroup\$ – Yann Vernier Jan 14 '11 at 7:27
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For the clock you use the DLL/PLL megacore.

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  • \$\begingroup\$ The spartan 6 has DCM and PLL's, not found DLL yet. After searching forums I found that the Xilinx has a tool called Core Generator that can be configured to generate clock resources. \$\endgroup\$ – Kevin Boyd Jan 4 '11 at 4:00

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