All Questions
4 questions
1
vote
1
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107
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Struggling to understand how a JK flip flop can behave contrary to understanding
I have tried to understand how the JK flip flop in the image below (U3B) is behaving, and I am at a loss.
For context, I've included related parts of the circuit. However, to avoid muddling my issue, ...
- 139
0
votes
0
answers
270
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Turn a positive clock edge into a negative pulse to make a 74LS170/670 register file synchronous
This is a follow-up o Why did they make the 74x170 (670) register file asychronous, no CLK input?.
I want to use that "register file" for my project, but I need to make it behave properly as a ...
- 1,669
2
votes
3
answers
246
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Deciding which assembly is more common positive edge detector
I know of two circuits which can act as edge detector:
A clock connected as a voltage source across a RC component where resistance is composed of a diode and a resistor and this in series with ...
- 279
2
votes
1
answer
682
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Reconize JK Flip-Flop operating edge: rising or falling?
This is a JK Flip-Flop image.
Using this image is there a way to know if the output changes on raising or falling clock? In other words, is input data
transferred to the outputs on the HIGH-to-LOW ...
- 210