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Tagged with programmable-logic ise
5 questions
2
votes
1
answer
1k
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New design with XC9500XL CPLDs, is it already obsolete?
I am in the middle of a new design for which a relatively small amount of logic is needed. This is a change to a previous version in which discrete 3.3V logic parts were used. We decided to go a CPLD ...
- 8,546
1
vote
1
answer
159
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Can I estimate what CPLD I need?
I'm planning to design a driver for VGA connectors, and for testing purposes I have an evaluation board of one CPLD. Concretely, the board is the Digilent's CoolRunner-II with the Xilinx's XC2C256 ...
- 191
2
votes
1
answer
489
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What is the purpose of a "BUF" in Xilinx ISE schematic?
I'm working on a schematic for a Xilinx CPLD using ISE. The schematic has a triangle symbol labeled "BUF" before every output, and also between some other nets. I can't really tell why some ...
- 23
2
votes
1
answer
198
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Using the UCF constraints to assign one of two output ports
I've got a CPLD design which has one spare (Debug) pin. I'm trying to find out if it's possible to use the UCF file to select which output port (NET) that pin becomes.
The problem is however, that I'...
- 349
2
votes
0
answers
233
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Macrocell and Function Block optimization ISE XILINX
I get the following result when I compile my code in ISE. It says the CPLD is full, but I can't help but notice that the optimizer should be able to move elements from different function blocks to ...
- 500