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Results tagged with fpga
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user 166884
A Field-Programmable Gate Array (FPGA) is a logic chip consisting of an array of programmable logic blocks and interconnects that is configured by the customer after manufacturing—hence "field-programmable".
1
vote
What does frame, word, and bit mean on a FPGA
For an image of m x n pixels, it contains mn no. of pixels. Pixel is said to be the smallest constituent of an image. If we say the picture is a 24-bit image, it means one pixel of the image is repres …
- 11k
1
vote
Using both Synchronous and Asynchronous resets in a design
If I have a design with synchronous reset, and you feed it with an async reset signal which may be asserted at any time, it internally goes via a clocked flip-flop. So for the design, it will be just …
- 11k
1
vote
Accepted
found '0' definitions of operator “*”
VHDL is strictly typed language as you know. You have a bit type conversion problem in that statement you assign to RESULT. It should be -
RESULT <= std_logic_vector(unsigned(Content(to_integer(unsig …
- 11k
6
votes
How to write scalable VHDL code
Declare data_width as generic in top module. Map this generic to corresponding generics in the submodules. For eg:
entity Top is
generic (data_width: integer := 32);
port (...);
end enti …
- 11k
3
votes
Accepted
Compatibility between TTL output and LVTTL input
Basys3 IOs are either LVCMOS/LVTTL (2.5 to 3.3 V). Refer datasheet.http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf
It would be unsafe to use 5V TTL to drive them …
- 11k
5
votes
1
answer
7k
views
Ranged vs Non-ranged Integers in VHDL
signal a: integer;
signal a: integer range 0 to 3;
Will the first choice take up a 32 bit register in the FPGA? …
- 11k
1
vote
Is it good practice to always assign initial value and reset signals in digital design?
Great post and everybody has given great answers here. A sync/async reset to initialise values, is always provided to be on the safer side, during power-on. This is especially true in case of ASICs. T …
- 11k
1
vote
Debounce on Nexys4 DDR button
The baud rate you have chosen is 9600 bps. Which means, your UART will take around \$ 1/9600 \approx 0.1 ms \$ to send one bit. Which means to send a complete frame with 8 bits, one start bit and sto …
- 11k
1
vote
VHDL - Adding two std_logic_vectors, issue
From the understanding of your requirements, you should be doing continuous assignment to overflow. i.e, outside the process as a concurrent statement inside architecture.
process ()
...
end process …
- 11k
2
votes
Accepted
How to read data from an .mif file in Vivado?
Seems like your file path is causing problem. Specify full file path to .mif file
Anyway Vivado will synthesise only a distributed RAM for your array music. To use Block RAM, you have to generate one …
- 11k
0
votes
Accepted
fpga gpio pins as uart pins (tx and rx)?
Make sure you have set the correct voltage level for pins in the GPIO expansion header to 3.3V
Refer to page 46
These pins have tolerance upto 3.7 V, hence you should be able to use your USB-TTL 3.3 …
- 11k
4
votes
Accepted
Signed number multiplication on FPGA
The Vivado synthesiser is smart. You have to declare the operands as signed. If the operands are unsigned, explicitly type cast all of them to signed and then simply multiply using *. It should infer …
- 11k
2
votes
Accepted
Setting Pulldown on the PMOD Pins (Nexys A7)
'PULLDOWN' attribute/property is deprecated. You can do it using 'PULLTYPE' attribute instead in Vivado. Either apply this attribute in your RTL code, or in the XDC constraint file. Writing in the XDC …
- 11k
8
votes
Can always @ (*) introduce randomness in FPGA?
Synthesiser perspective
Secondly, * has nothing to do with Synthesiser, because Synthesisers ignore the sensitivity list ahead of implementation on an FPGA/ASIC. … values on FPGA on-board, you might want to take a look at LFSRs on FPGA. …
- 11k
1
vote
What is scope of variables in Verilog modules?
Signals declared inside a module have their scope local to that module only. So, yes, two different modules in a source file can have signals with same name, with corresponding local scopes.
However, …
- 11k