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Results tagged with cmos
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user 90588
"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.
13
votes
Preference of BJT to MOSFET
CMOS transistors on an integrated circuit can be much much smaller (1000's of times) than BJTs. … BJTs have more precision and specialized uses in some analog circuits, but modern CMOS processes can approach their performance. …
- 20.4k
8
votes
Determining how much load capacitance a 40-series logic IC can safely drive
Therefore you power is ½.C.V^2.f
CMOS ICs are no intended to operate at maximum power dissipation continuously, and there can't be a real guarantee of long term (years) reliability under this condition …
- 20.4k
4
votes
Please help me explain the overshoot and undershoot in CMOS inverter
As the input signal starts to rise from 0 V, the NMOS transistor in the inverter will turn on when it reaches a threshold voltage; as it rises further, eventually the PMOS transistor will turn off.
I …
- 20.4k
4
votes
Accepted
CMOS differential pair - common-mode rejection ratio
Remember the ISS current is constant. With different gm's, the transistors may run different DC currents (which sum to ISS). Since you assume ISS is constant, and there are no body effects or ROUT eff …
- 20.4k
3
votes
Accepted
Level shifting in HV CMOS processes
Most technologies are limited to VGS < 10 V, or 5 V in more modern ones, and need circuits like this. High voltage level shifters are needed in high voltage DC/DC converters and similar circuits.
Th …
- 20.4k
3
votes
How do the dimensions of a MOS tranistor affect the gain of a CMOS inverter?
The gain depends on the ratio of output impedance to gm of the MOSFETs. gm depends on W/L (at a given bias current), and is fundamentally quite similar for both circuits. However output impedance incr …
- 20.4k
3
votes
Why is this circuit a two-stage amplifier?
It is not called a two-stage amplifier in any common usage.
It is a single stage differential amplifier because there is a single node where voltage gain occurs -- at the drain of MN1. The signal ther …
- 20.4k
3
votes
Clock feedthrough in 5T OTAs?
When VREF drives the gain node (M2), you get feedthrough from the output to the G of M2 as the output toggles.
If you exchange inputs, then VREF only drives a diode-connected M3, and the swing there i …
- 20.4k
3
votes
Accepted
Why there is no shoot-through in CMOS logic gate?
In normal CMOS circuitry, the input signal transition is quite fast. Therefore the time during which both devices are (partially) on is quite small. … In CMOS circuits the current wasted by shoot through is usually smaller than that wasted by charging (or discharging) the load capacitances. …
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2
votes
Prevent spikes during transition of inputs in AND gate
CMOS logic gates with such inputs are CD4093 (quad NAND), and CD4584 (hex inverter). Once you have 'squared up' the inputs, you can use them with standard logic gates. …
- 20.4k
2
votes
Variation in Tphl of MOS nand gate due to input patterns
There is no guarantee in a digital library that the A and B FETs are the same size; they can be optimized for different performance.
When you have a A=1; B 0->1 transition, the output may initially go …
- 20.4k
2
votes
Accepted
Op Amp design - open loop gain 73dB, closed loop gain -200dB
Your open loop gain has a phase of -180 deg. Your VIN+ and VIN- labels are reversed.
This is not a good way to measure AC open loop gain; in general you can't get a good bias point, although it seems …
- 20.4k
2
votes
How to measure the retention time of a capacitor?
Build it and simulate. The capacitor model should include leakage, but if it does not, you will have to find the technology description, oxide thicknesses and lookup the general leakage characteristic …
- 20.4k
2
votes
Accepted
channel length in Cadence
They can be different.
Usually in logic circuits, the optimal size (for sped and power consumption) is to have all devices at minimum allowable channel length -- the widths may differ.
For analog c …
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1
vote
What is the meaning of Bootstrapping Phenomenon in MOSFET,What are its Consequences & How to...
Bootstrapping is not really the correct term for this.
MOSFETs all have capacitance between the gate and drain. While some is a parasitic due to the wires, most of it comes from the actual structure …
- 20.4k