Prevent spikes during transition of inputs in AND gate

Question

Question

Suppose we have a two-input AND gate. The inputs do not change instantly. So, it's not a perfect rectangular signal rather trapezoidal.

Consider the situation when input 1 is transiting to the LOW state while input 2 is transiting to HIGH, there is a short instance of a time when both of them are HIGH and hence, there is a spike in the output of the AND gate.

1. What electronic circuit or methodology can we use to get rid of these spikes?

2. Is there a definite terminology for this problem?

Plots

What I have:

What I require

Background

I am currently working on a Project. The terms that I used here may not be accurate so do pardon me, and correct me if possible. Thanks in advance.

Answer 1

There's nothing that can be done to eliminate output spikes in this circuit.

The AND gate is suffering from an 'internal race condition'. This would often be referred to as a 'decoding spike', as they are most frequently met when an address word goes into something like an 74HC138 address decoder, and two address bits transition simultaneously.

This isn't a fault, it's perfectly normal. Logic gates are not defined or designed to do anything reasonable when the inputs are between the logic thresholds. They are defined to output the correct logic state some short time after the last input's transition to a valid state.

These sort of spikes are tolerated all the time in clocked systems. On one clock edge, the changing (usually address) bits are sent to the combinatorial logic. For a while, the outputs will slew, and spike, and eventually settle down. On the next clock edge, when the outputs are stable, they will be clocked into the next stage of processing. It's the job of the digital designer to make sure there's enough time between clock edges for the outputs to stabilise.

If you want to use the outputs directly, and can't lowpass filter to suppress the spike, then you must takes steps to skew the inputs. This is the reason Gray Code was invented, and Johnson counters have this property too, that unlike straight binary counters, only one output makes a transition on any clock edge.

Answer 2

It looks like your intended gate is not an AND gate, but a gate where output = (IP1 AND NOT(IP2)).

It is possible to make the input transitions faster and more clean to the gate, but basically you have an indeterminate condition when both inputs are (slowly) transitioning simultaneously. Because the logic gate has no memory, its output basically depends on only the instantaneous values of its inputs. With inputs transitioning, it is not clear at what point it should be considered a '1' or a '0'.

You can clean up the inputs with a Schmitt trigger input. This does have a memory and it operates such that with a slowly rising input, the output changes only when the input exceeds a certain threshold. When the input is falling, it changes only when the input falls below a lower threshold. This is called hysteresis.

CMOS logic gates with such inputs are CD4093 (quad NAND), and CD4584 (hex inverter). Once you have 'squared up' the inputs, you can use them with standard logic gates.