Register Transfer Level (RTL) is a logic design abstraction where digital circuits are described in terms of storage elements (registers) and the combinatorial logic operations that occur between them. RTL is one way of describing a system in hardware design languages such as VHDL and Verilog.

Register Transfer Level is an intermediate level of abstraction that is used to describe synchronous digital systems, in which the key elements are the storage elements (registers and memories) that constitute the "state" of the system, and the combinatorial logical and arithmetic operations that connect the register outputs to register inputs.

Other levels of abstraction include "structural", in which the logic is described directly in terms of the physical elements (gates and flip-flops) used to construct the system along with the wires that connect them, and "behavioral", in which the overall behavior of the system is described in the most convenient manner.

RTL is commonly used for logic design because it is abstract enough to avoid bogging down the designer with the minutiae of implementation details, while still being able to be automatically translated (a process called "logic synthesis") to a structural representation in one or more implementation technologies (e.g., FPGA or ASIC).

Automatic translation from a behavioral model is often difficult or impossible, but behavioral code can be used to build simulation "testbenches" and "breadboards". A behavioral model of a module can later be compared with the corresponding RTL or structural model in order to verify the correctness of the implementation.

Hardware description languages such as VHDL and Verilog can be used to describe systems at all three levels of abstraction.

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