0
\$\begingroup\$

Is the expression (BC + AD)<<16 equivalent to (BC << 16) + (AD <<16)?

From some examples which I tried it seems to be true but not sure at all

\$\endgroup\$
3
  • 2
    \$\begingroup\$ << means shift . \$\endgroup\$
    – MrCalc
    Dec 26, 2020 at 19:14
  • 2
    \$\begingroup\$ Not necessarily. It depends on the width of the signals, and how the synthesis tools decide to expand the widths of BC and AD in the event of the bitshift. \$\endgroup\$ Dec 26, 2020 at 19:34
  • \$\begingroup\$ @TomCarpenter, will different synthesis tools behave differently? If that is the case, there would be a mismatch between simulation and synthesis. According to Intel's documentation, the width is extended to the size of the output, and that was also what I observed in simulation \$\endgroup\$ Dec 28, 2020 at 5:25

2 Answers 2

7
\$\begingroup\$

They are equivalent. The width of all operands get extended to the size of the largest operand before any operation occurs. As long as the width of one of BC or AD is 16 bits wider than the value being shifted, then what you wrote is mathematically equivalent to

\$(BC + AD)×2^{16} = BC×2^{16}+ AD×2^{16}\$

If the width of the largest operand is not wide enough to hold the shifted value, then it gets truncated to that width.

\$\endgroup\$
2
  • \$\begingroup\$ "As long as the width of one of BC or AD is 16 bits wider than the value being shifted" - What does value refer to here? \$\endgroup\$ Dec 27, 2020 at 4:37
  • 1
    \$\begingroup\$ The magnitude of the value stored in BC or AD. \$\endgroup\$
    – dave_59
    Dec 27, 2020 at 4:45
1
\$\begingroup\$

Yes, as long as the width of the left-hand side you are assigning to is the same in both cases.

If the width of the left-hand side is smaller than the right-hand side, the value will be truncated to the Least Significant bits. In other words, the Most Significant Bits are discarded.

The width of the operands are extended to the same size as that of the largest operand, and then the operations are performed. When extending the operands on the right-hand side, zeros are filled in the Most Significant bits, and then the operations are performed.

In the case of the addition operator, the operand includes the left-hand side. The width of the left-hand side is fixed.

\$\endgroup\$
1
  • \$\begingroup\$ If the question is about Verilog then the important documentation would be the Verilog IEEE standard rather than any single vendor's documentation. It is dangerous to assume that all Verilog tools behave in exactly the same way unless the standard says they must. \$\endgroup\$ Dec 28, 2020 at 13:04

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.