How would a 4-bit full-adder be implemented in a Cyclone V FPGA?

Question

I have this diagram from my class of how 3 6-input LUTs are used to create a Full 4-bit adder. It's not particularly clear, but each 6-input LUT has 2 outputs (so I suppose they're really operating as 3 groups of pairs of 5-input LUTs?). Also, one of the 6-input LUTs is visually split into 2 pieces (Add1:Ad0 and Add1:Ad2).

The ALM for a Cyclone V actually has an 8-input LUT that can have 4 outputs (so 4 6-input LUTs in a way).

In trying to figure out how the 4-bit adder was implemented in with this ALM, I am perplexed by:

1. what the purpose of the "full adders" would be if the LUTs can seemingly do the job of adding
2. The implementation above requires the Logic to be carried out in 2 different timing intervals because the 2nd interval relies on the carry bit from the first interval (Add1:Ad1)

So how might a 4-bit adder be implemented using this (admittedly vague) ALM? I would greatly appreciate if you could answer with particular attention to addressing my points of confusion.

Answer 1

what the purpose of the "full adders" would be if the LUTs can seemingly do the job of adding

but at a high "price", as you can see. Since adding "carry-overs" and similar concepts are so common a thing, having an extra path for adding another bit to the output of a LUT helps implement a lot of functionality in less space.

The implementation above requires the Logic to be carried out in 2 different timing intervals because the 2nd interval relies on the carry bit from the first interval (Add1:Ad1)

You can of course add two 4-bit numbers in a single clock cycle cobinatorically. It might just be reducing the maximum clock rate and/or need more space. (However, if adding two 4 bit numbers is your deepest combinatorial path, you're probably doing rather well.)

Answer 2

1. n/2 Cyclone V ALMs can do n-bit addition, even with three summands - I presume with carry in. For even n, I do not see how to get a carry out other than using one more ALM adding zeroes.
   This would probably still be faster than not using the built-in addition support.
   Not using the built-in addition support may have instructional merits.
2. S[3] and Co depend on 9 input signals. Without LUTs with at least 9 inputs (big as of 2024), there is no way to generate them without cascading LUTs/ALMs.

To gauge the capabilities of a Cyclone V ALM, I stare at the detailed diagram Intel provides for ALM outputs:
To the right I see four outputs to non-local routing, two to local routing, and bottom-left two that seem to directly connect to the "below" ALM (shared_arith_out & carry_out). (It must be possible to drive the corresponding inputs differently. I found nothing on using these latter outputs directly.)
From "the LUT part" (left of the vertical clk, load&clr routing) to the register part, there are just two signals from LUTs(&adders) (+ datae/f0/1).
There are two groups of LUTs, each shown with one 4LUT and two 3LUTs.
There are two selectors fed by both 3LUTs allowing to independently combine the 3LUTs output signals for use in further selectors or in the adder.
This can be used to operate them as a 4LUT.
There are "downstream" data selectors allowing to combine them with the 4LUT in the group for one 5LUT per group.
I do not see how to combine both for even a single 6LUT inside the same ALM, for general functions of more than 5 inputs.