I have a simple question about the sensitivity list. I read it on some books. It said that the sensitivity list is only important for the simulation. I don't quite understand. Does that mean, if I remove the sensitivity list, for the emulation on a actual FPGA it won't matter. If I remove the sensitivity list, how does the FPGA know when a process is triggered?
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1\$\begingroup\$ That's a bit confusing subject. Sometimes synthesizers are relying on the sensitivity list. Sometimes they don't. So the golden rule is to include all of the signals the process is sensitive to for both, simulation and synthesis. Take a look here:stackoverflow.com/questions/8991223/… \$\endgroup\$– Eugene Sh.Commented May 17, 2017 at 16:25
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\$\begingroup\$ @EugeneSh. I also think the safer way is to include the signals in the sensitivity list. Thanks for the answer. \$\endgroup\$– S. LiCommented May 17, 2017 at 16:33
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3 Answers
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Usually, the simulator cares about the sensitivity list. But the synthesizer does not. The purpose of the sensitivity list is to let the simulator know that a process only will change its outputs if one of the signals (A, B, C) changes. That lets the simulator run more efficiently. However, the synthesizer usually doesn't look at the sensitivity list; it just looks at the process's body.
If you simulate a circuit, but leave important signals out of the sensitivity list, then sometimes the simulator will give you the wrong answers. That means your final FPGA or ASIC will behave differently than the simulator.
If you put extra signals in the sensitivity list, then the simulator will give you the right answers, but run more slowly.
So, the only thing the sensitivity list is for is to let the simulator run faster. It's a hint to the simulator, so it can run more efficiently. But the simulator and the synthesizer can ignore the sensitivity list, since it's just a hint.
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Keep in mind that the "process" does not actually exist in the FPGA. The process is merely an abstract description of the behavior of a chunk of hardware. The synthesis tools create that hardware based on the behavior specified in the source code, including any process blocks. The actual hardware will do what it does continuously.
In VHDL, anything that must be controlled by an edge on a signal (e.g., a clock) must be explicitly specified using 'event qualifiers on signals as conditions inside a process (possibly hidden inside a function such as rising_edge()). This is completely independent of the sensitivity list of the process itself, which is indeed used only to trigger the evaluation of the process in a simulator.
Note that this is very different from the sensitivity list associated with a Verilog always block, which is a conflation of the two concepts that VHDL keeps separate.
answered May 17, 2017 at 21:24
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Sometimes sensitivity list is only important for the simulation,if you lost a signal in sensitivity list you may get the wrong simulate answer.But the real FPGA function will right if your logic is right.
You can called it ‘pre-sim and post-sim inconsistent’.
The real scared thing is your pre-sim is right but your post-sim is wrong.That will cause your FPGA function wrong.
