How does the AXI-Interconnect know where to route the data?

Question

Im interested in where exactly the Addresses (BASE_ADDR) set in the "Address Editor" of a Vivado Block Design come into play in the FPGA-Part. I have multiple Blocks with AXI-Lite connected to a Zynq via an AXI-Interconnect, which works fine. But i want to know how:

To my current understanding, the routing must be somewhere in the AXI-Interconnect-IP-Block, however i can not see how it knows where to route the bus as "Customize IP" shows nothing related to the Addresses. It just seems to magically connect everything correctly...

So how does it work?

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Edit: For clarification - this is how the part of my system looks like:

                       ______________         
                      |              |---------- Block 1 (AXI-Lite)
                      |    AXI       |---------- Block 2 (AXI-Lite)
Zynq (AXI Bus) -------| Interconnect |---------- Block 3 (AXI-Lite)
                      |              |---------- Block 4 (AXI-Lite)
                      |______________|---------- Block 5 (AXI-Lite)

The Zynq itself is not relevant in this picture, there is just a full AXI-Bus on the left and multiple AXI-Lite-Blocks on the right, which can have Address-Ranges set in the "Address Editor" of Vivado.

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Further clarification: I know how the lower bits of the address-lines are used to address single registers in AXI-Lite, but the Xilinx-Template doesn't seem to care about the higher bits, therefore my assumption that the addressing has to be done outside of the AXI-Lite block.

Answer 1

The address decoder is inside the interconnect. There are parameters at some level inside the IP block that set the addresses. Maybe they are not exposed at the top level as I think the top level file is generated, but they are in the heirarchy somewhere.

Answer 2

The bus is physically routed to every block that needs access to it. Each block is responsible for decoding its own addresses, which is why each one has a "base address" setting. It's up to you to make sure that the address ranges don't overlap.

Answer 3

Your diagram helps.

The AXI infrastructure is a 'star' network, not a 'bus'.

The reason is that AXI uses a handshake protocol (valid and ready) for each transfer. These are paired with every valid having one ready. (You can't give out many valids and wait for any ready to come back).

Thus if you have one AXI bus going of to many destination you need a to make a dedicated AXI stream with it's own valid and ready. Thus is done inside the interconnect. The address is used to decide to which output port the transaction should go. Therefore the address decoder you are looking for is inside the AXI interconnect.