Can I program a platform independent PLL in VHDL?

Question

Most FPGA developement boards have a 50 MHz clock source onboard. However, the FPGAs are typically able to work faster than this. For multiplying the clock speed it seems to be needed to use a custom vendor specific IP of the FPGA, that must be configured and placed in the design.

Is there a way around this? Can I program/define my own PLL in VHDL, that is preferably synthesized using the internal hard coded PLL blocks of the FPGA and works for Altera and Xilinx without having to manually insert the PLL to a project via MegaWizard & Cons?

Answer 1

You can do this by including vendor specific primitives in your code.

Both Xilinx and Altera have PLL primitives that can be instantiated in the source code with no gui.

Xilinx: PLL2_ADV and PLL_BASE (from page 351 onward)

Altera: altpll User guide

While the Altera AltPLL IP does have a gui (and they highly recommend you use it, due to the wide range of PLL configuration parameters they have available), you don't actually have to use the GUI. Or, you can use the GUI once and then just keep the vhdl file it generates. I tested this by removing the IP gui file (.qip) from the project and added the source only, and it synthesized fine.

In both cases, you'll need to include the libraries at the top of your code.

-- Altera
LIBRARY altera_mf;
USE altera_mf.all;


-- Xilinx
LIBRARY UNISIM;
USE UNISIM.vcomponents.all;

The biggest issue is differentiating between vendors. The --pragma directive doesn't have a way to distinguish between vendors, so you'll need to use generate statements to do so. See this answer for more info about that: what is #define equivalent in VHDL