If A=0, B=1, and x=0 what are A' and B' in the logic circuit below?

Question

The following circuit diagram what are A' and B'?

The question in the slide asks what happens if A=0, B=1, and x=0.
I understand what it means when x=0, but what exactly does this mean when A=0 and B=1? The way A and B are labeled in the diagram it appears like they represent the hardware device, not an input. Can someone explain to me what A and B are exactly?

In the following diagram we are given the answer if A=0,B=1,and x=0 in red. Can somebody explain how they arrived at this answer?

Trying to make sense if it myself, here is my train of thought:

Input x is fed into a NOT gate, making it x'. x' is fed into an AND gate with Q', thus making the output (x'^Q'). Which is then fed into an OR gate with Q, giving you Q OR (x' ^ Q') = (Q OR x') AND (Q OR Q') = Q OR x'. This is fed into both inputs of B, which doesn't make any sense to me. At this point I am lost, so I would appreciate some guidance what happens to Q OR x'?

Answer 1

A and B are D latches; on the clock edge, the value on the input is latched to the Q output.

A = 1 means that the Q output associated with the A latch is high (the complementary output is thus low).

A = 0 means that the Q output associated with the A latch is low (the complementary output is thus high).

A' is the value of A after the next clock edge.

This is a state machine. A and B represent the current state. The current state, along with the input x, determine the next state denoted by the primes on A and B.

So, for example, the input to the A latch is x so, if x = 0, on the next clock edge, 0 will be latched, i.e., the Q output of the A latch will be low; A' = 0.

Following the logic, the input to the B latch is: \$(\bar x \cdot \bar A) + B \$

So, for x=0, A = 0, B = 0, the input to B is 1 and thus, after the next clock edge the Q output of B will be high; B' = 1.

UPDATE: a closer look shows that the schematic does not match the state transition table. It's obvious that the input to the A latch is x and so, A' = x according to the schematic. However, the 5th row in the state transition table has A' = 1 when x = 0. That's not consistent.