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Below is a CMOS circuit for an inverter (or NOT gate). According to the book I am reading, when \$V_{x} = V_{supply}\$, \$T_{1}\$ will be turned off and \$T_{2}\$ will be turned on. So \$T_{2}\$ will pull the output \$V_{f}\$ down to 0.

But I have been wondering, since \$T_{1}\$ is turned off, there will be no current from \$V_{supply}\$ through \$T_{1}\$ to \$V_{f}\$. If I consider \$T_{1}\$ as a resistor, there will be no voltage drop through it. So why \$V_{f}\$ choose to be 0 rather than \$V_{supply}\$ ? I guess I missed some important concept.

enter image description here

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Don't forget that T2 is also a resistor. When T2 is on it is a very low resistance resistor (pretty much a short-circuit). So what is Vf if T1 is a very high resistance and T2 is a very low resistance?

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  • \$\begingroup\$ Wow, a typical divider, right? \$\endgroup\$
    – smwikipedia
    Commented Sep 1, 2020 at 3:49
  • \$\begingroup\$ @smwikipedia Yes. A divider where the top resistor is very very high and the lower resistor is practically zero. Try not to use the "zero current through a resistor means the voltage on both sides of the resistor is the same" unless it's a dead end connection not connected to anything else. And if it's a very high resistance this might also not be true since the resistance is so high that equalizing charge has trouble flowing across the resistor have trouble flowing so any EMI will be picked up and read on the dead-end node since the charge build up takes time to drain through the very high R. \$\endgroup\$
    – DKNguyen
    Commented Sep 1, 2020 at 3:49
  • \$\begingroup\$ Thanks for the elaboration. Btw, what is EMI ? \$\endgroup\$
    – smwikipedia
    Commented Sep 1, 2020 at 4:48
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    \$\begingroup\$ @smwikipedia Electromagnetic interference \$\endgroup\$
    – DKNguyen
    Commented Sep 1, 2020 at 17:50
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Please be careful when using the LTI equivalent for transistor devices. It makes sense in analog electronics where one may extract rather accurate limits for small signal modelling; OTOH, in digital electronics such approximation can be rather crude and misleading.

When a logic \$V_x = 1\$ is applied to both transistors' gates, T2 has sufficient \$V_{GS}\$ to form a minority inversion channel, whereas T1 won't (MOS will be in accumulation). You can think the channel to electrically connect the Source and Drain terminals: a sort of short between them.

Now, if T2 has its source at ground, such connection will take \$V_f\$ to ground as well -- namely acting as a what's usually called a PDN. T2 will be in triode with \$V_{DS}=0\$ and this agrees with \$I_{DS} = 0\$. Also notice that T2 will be working on its highest VTC, thus capable to sink the largest current. T1 will be in cut-off and will be working on its lowest VTC, even though \$V_{SD} = V_{supply}\$.

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