Is it possible to use an if then clause within a for generate clause in VHDL?

Question

I am trying to use an if then clause within a for generate in VHDL but it does not compile:

first_row: for j in 0 to 5*2-2 generate
if (j=5*2-2) then
i_fa_first_row: full_adder_std_logic port map(ai=>sum_ini(j),
                         bi=>zero,
                         ci=>mul(0,j),
                         si=>sum(0+1, j),
                         co=>c(0+1, j+1));
end if;
end generate first_row;

Nonetheless it does compile when I take the conditional clause out of the for generate clause. Does anyone know whether it is possible to do what I am trying to do?

Answer 1

This is a conditional instance, you need to use if ... generate syntax for that.