I'm working on a prime calculation project which is to be implemented using Verilog on a Zybo board. I'm currently facing a strange problem and looking for a method to way forward. I have implemented an FSM with 12 states. In my FSM, I set a register called 'flag' to LOW at state 'S2' and it is set to HIGH at state 'S10'. All simulations, including Post-implementation Timing Simulation, give results as expected. However, when implemented on the hardware it doesn't give expected results. After many days of troubleshooting, I found(using Integrated Logic Analyzer) that the register 'flag' stays HIGH only at state 'S10'. It works like I had assigned a default value for 'flag' as ZERO and change to HIGH when it is at state 'S10'. But that is not what I have coded. Any idea or suggestion to solve this issue would be highly appreciated.
The relevant Verilog code is given below.
// Output logic
always@(*) begin
idle_reg = 0;
ld_A = 0;
ld_n = 0;
ld_i = 0;
ld_P = 0;
clr = 0;
start_mod = 0;
prime_found = 0;
done = 0;
case(state)
WAIT: begin
idle_reg = 1;
clr = 1;
end
S1: begin
ld_A = 1;
ld_n = 1;
end
S2: begin
flag = 1'b0;
ld_n = 1;
end
S5: begin
ld_i = 1;
end
S7: begin
start_mod = 1;
end
S10: begin
flag = 1'b1;
end
S11: begin
prime_found = 1;
ld_P = 1;
end
DONE: begin
done = 1;
end
endcase
end
