Computers: How signals in the bus can travel in either direction [closed]

Question

I'm reading J. Clark Scott's book But How Do It Know.

When he is describing registers and the bus he illustrates this at one point as five registers sequentially parallel-connected to a bus.

As you turn on the enabler of one register all other registers will copy its byte if their signal is turned on.

If R3s enabler is on it sends signals both left and right, to R2 and R4, and all other registers.

My assumption: The bus is a loop connected to ground at the end so the current from R3 that is sent on the bus has parallel paths to ground, left and right.

My question: Is the bus connected to ground in both directions, and how is the current maintained on the bus when it is being split into the each registers' inputs?

Answer 1

• Instead of thinking of currents think of voltages.

Figure 1. Computer architecture showing address, data and control busses. Source: Wikispaces.

• Remember that "bus" is short for "omnibus" (Latin) which means "for all".
• If any device applies a voltage onto the bus then all others connected to the bus can see it and read it.

... how is the current maintained when it is being split into the the other registers' inputs?

Each logic device will have a rated output "fan-out" which tells you how many inputs can be fed from that output. This used to be a big issue with TTL logic which had high input currents but isn't generally an issue on CMOS as the input resistance is so high that negligible current is drawn (other than to charge up the input capacitance). You can generally consider the inputs as voltage driven.

It might be worth noting that each device on the bus will load the bus whether enabled or not because the enable/disable feature will be implemented after the input buffer (which is what creates the bus load).

See my answer to What is a bus (physically) in digital design? which has more on the topic.