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Question

I'm trying to make a component model for the LH0063 single ended line driver in LTspice... The propagation delay is the dominant parameter for the frequency response but I'm having a hard time modeling it.

I'm using the 'Universalopamp2' component as a voltage follower... I see there are different levels(versions) to this component. Is there a way I can configure this model's parameters to simulate the propagation delay?

About the part

from the datasheet:

  • Bandwidth: 100MHz
  • SlewRate: 6000V/us

From bench testing, the Slewrate is real but the Bandwidth is not... The propagation delay attenuates the signal. The part has a propagation delay of ~5ns .

  • An input square-wave signal of 25MHz(Tp=40ns), will be shifted by 5ns (45degress phase shift).
  • An input sine-wave signal of 25MHz(Tp=40ns), will be shifted 45degress and will be attenuated by -3db.

Looks like this on the bench:

Looks like this on the bench.

Datasheet frequency response:

enter image description here

LTspice Model attempt

I tried to introduce the prop-delay using a transmission line (tline). The problem is tline also limits the edge rate, rather than just causing a delay:

enter image description here

Here is the simple versions I made (don't care about Bandwidth): enter image description here

This I my attempt using tline to introduce the delay, mediocre results.

enter image description here

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    \$\begingroup\$ Doesn't LTSpice have a thing called an analogue delay macro (as per micro-cap)? \$\endgroup\$
    – Andy aka
    Commented Sep 15, 2022 at 18:02
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    \$\begingroup\$ Set your maximum timestep in the .tran statement to something like 1p. You can also try the delay or absdelay functions with a B-source, but I think you'll have the same problem. See the "B. Arbitrary Behavioral Voltage or Current Sources" section of the LTspice help for syntax of those functions. \$\endgroup\$
    – Ste Kulov
    Commented Sep 15, 2022 at 18:31
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    \$\begingroup\$ @Tony #fakenews. Can you show an example of it not working? Or clarify what specifically doesn't work? Because I can show the opposite. My group delays match. i.sstatic.net/ihrRZ.png \$\endgroup\$
    – Ste Kulov
    Commented Sep 15, 2022 at 18:45
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    \$\begingroup\$ Use level.3b with appropriate settings and you should get a built-in analog delay, which may be better than the tline due to the continuous nature of the tie response. Here's a quick test. \$\endgroup\$
    – a concerned citizen
    Commented Sep 15, 2022 at 18:54
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    \$\begingroup\$ You gave no feedback on my suggestion of universally reducing the maximum timestep, so I'll assume you don't like it because it slows the simulation down and the user of your subcircuit needs to know to reduce it. One way around that is by forcing a timestep reduction based on the signal slew. You can use tripdv and tripdt parameters of a B-source to do this. You can actually still use the tline for your signal path (if you prefer; you still haven't explained why) and throw the B-source off to the side, since its sole purpose would be to force the timesteps for the rest of the circuit. \$\endgroup\$
    – Ste Kulov
    Commented Sep 16, 2022 at 7:48

1 Answer 1

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I don't know how your Tline model works.
Seems also that the steps used are too large (I used 1 ps).
I don't have LH0063 in my database, so I took another opamp (AD8009).

Here is what I get. TRAN Analysis

enter image description here

AC Analysis, with Group delay.

enter image description here

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