Propagation Delay of Sequential Logic Circuit

Question

I'm trying to work through the above sequential logic problem from MIT OCW's Computation Structures course. However, I'm having trouble calculating t_pd of the Zero output.

I'm a complete novice at this, but I thought that when calculating t_pd of a system like this, you calculated t_pd of the longest possible path.

However, the answer key says that the answer is simply t_{pd, DREG} + t_{pd, NOR3}, so 0.19 + 0.08 = 0.27. Why would the t_pd of the logic and the MUX not be factored in to this calculation?

Answer 1

Why would the tpd of the logic and the MUX not be factored in to this calculation? Blockquote

Those parameters would affect whether or not the input setup and hold times for the DREGs were met, but have nothing to do with the output delay (unless a metastable condition arises).

Those parameters would also affect the maximum clock rate that could be achieved, since the output of the DREG is being fed back into the combinatorial log, who's output (through the 2:1 MUX) is the input to the DREG.

So the ZERO output prop delay is relative to the CLK only, and includes the clock to output delay of the DREG and the propagation delay through the 3-input NOR gate, as the correct answer says.