VHDL: Assigning type to specific value

Question

In VHDL, if I take create a type like this

type example is (
    ex_0,
    ex_1,
    ex_2,
    ex_3
);
signal example_signal : example

Then ex_0 would synthesize to something like '00', ex_1 to '01' , ex_2 to '10', and ex_3 to '11'. Maybe it'd be gray code but I don't know.

Is there a way to assign each of those to a specific value? For example it would look something like

type example is (
    ex_0 := '11',
    ex_1 := '10',
    ex_2 := '01',
    ex_3 := '00'
);
signal example_signal : example

Answer 1

The VHDL-2008 standard defines in chapter 5.2.2 enumeration types and says this:

Each enumeration literal yields a different enumeration value. The predefined order relations between enumeration values follow the order of corresponding position numbers. The position number of the value of the first listed enumeration literal is zero; the position number for each additional enumeration literal is one more than that of its predecessor in the list.

However, it specifies no way to assign deliberate values.

Answer 2

If you don't mind not using the enumeration, it looks like this:

constant ST0: std_logic_vector(3 downto 0) := "1000";
constant ST1: std_logic_vector(3 downto 0) := "0100";
constant ST2: std_logic_vector(3 downto 0) := "0010";
constant ST3: std_logic_vector(3 downto 0) := "0001";
signal PS, NS : std_logic_vector(3 downto 0);

But with enumeration, it looks even uglier (IMO):

type state_type is (ST0, ST1, ST2, ST3);
attribute ENUM_ENCODING : STRING;
attribute ENUM_ENCODING of state_type: type is "1000 0100 0010 0001";
signal PS, NS : state_type;

Which works in every synthesis tool I've used. For FSMs, at least, I've seen very good optimizations from Vivado (to the point of eliminating a DFF from a "One Hot Encoding" state).