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I'm trying to design a 59 second countdown on Quartus Prime, using a 4-bit JK stage for the second units and a 3-bit JK stage for the second tens. However, I've run into what I feel is a simple problem but can't quite find the right logic to solve it.

As I've just come to realize, Flip-Flops have a default value of 0, which creates a problem for my count visualizer in a 7-segment display. I realize I have to use the PRN input to preset the initial value (9 and five, respectively), but I don't know how to disable this line once the count actually begins (first CLK rising edge).

Now, I'm sure there's probably easier ways to do this, but I am in an introductory course, this is my first time working with this stuff.

I've attached an image of the Schematic I'm working on to get a better idea of what's happening.

Schematic of the second tens countdown circuit

ETA: The 'frec_div' block (as the name suggests) is a simple code where I divide the Cyclone IV's frequency (50MHz) to 1 Hz.

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    \$\begingroup\$ Flip-flops don't have a default value, they can assume any value immediately after power is applied. A simulator may suggest predictability, but real flip-flops have no guaranteed start-up value. That doesn't answer your question, it's just FYI. \$\endgroup\$ Commented Oct 21 at 5:14
  • \$\begingroup\$ Huh, interesting. Then is my board's display showing a 0 before starting the count because there just isn't an assigned value to Y[3..0] yet? And thanks, learning about this stuff is quite interesting! \$\endgroup\$ Commented Oct 21 at 5:24
  • \$\begingroup\$ Perhaps I spoke to soon, using an FPGA to implement JK flip-flops could guarantee a starting state, since the device will have an initial reset cycle, but discrete flip-flops (such as you'd find in a 7474) do not. \$\endgroup\$ Commented Oct 21 at 5:28
  • \$\begingroup\$ And even a reproducible initial state of discrete flip-flops may be just a result of the specific circuit. \$\endgroup\$ Commented Oct 21 at 5:45
  • \$\begingroup\$ @SimonFitch That's why you use a 7476 in a discrete system requiring a known power-up state. (As I did when building my first computer in 1974.) \$\endgroup\$ Commented Oct 21 at 5:54

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You need an additional input, "reset."

It is applied at power-on and optionally by user action. The counters start counting only after its deactivation. See below for details.

Use this to preset your flip-flops.

Nearly all digital designs use such a signal to initialize at least relevant parts. There is commonly no need to initialize each and every flip-flop.

There are two kinds of reset:

  • An asynchronous reset sets the concerned parts immediately to their initial state.
  • A synchronous reset sets the concerned parts at the next clock edge to their initial state.
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