Enable clock for a state machine?

I have 100Mhz system clock and I would like to have a 200Hz Enable signal for enabling the state machine. I need a clock divider for this process and thought about this :

clkdiv : process (clk)
begin
if (clk'event and clk = '1') then     -- rising clock edge
-- default value
EN <= '0';

clkcntr <= clkcntr - 1;
if clkcntr = 0 then
clkcntr   <= X"7A120"; -- 500000 decimal value
EN <= '1';
end if;

end if;
end process clkdiv;


I have seen other implementations on the internet they always start first dividing with 100Mhz to 2. In my case I should decrement 250000 time to match this, is this because clk is 1-0-1-0-1-0-1-0, since we are interested on the rising edge we should also consider the falling edge times? I would be glad if someone can demonstate a proper clock divider. Then when I am done I would like to go into the state machine with an if condition

if EN = '1' then

go into the state machine

end if;


In the end I would like the duration of my output signal from the FSM be 200Hz long, would this be correct? Are there other ways for implementing this?

• Do you want one pulse of a signal every 200 Hz, or do you want a signal to go high for 100 Hz, and then low for 100 Hz? – Bill Lynch May 13 '14 at 14:56
• @sharth I want an 200 Hz enable signal for solving the debouncing of a keypad. If it waits 200Hz long then there wouldnt be a problem. So every press should wait 200 hz... – Anarkie May 13 '14 at 16:09
• @sharth and Anarkie: What do you mean "high for 100 Hz" and "waits 200 Hz"? That doesn't make any sense. – Joe Hass May 13 '14 at 16:51
• @JoeHass: At first, I thought Anarkie wanted to create a 200 Hz clock from the 100 Mhz clock. Then, after re-reading, I thought that the desire was for to create a pulse every 200 Hz. Then, with the most recent comment, I started to believe that neither of those things are what is being asked here. – Bill Lynch May 13 '14 at 17:11
• If you want a 200Hz clock signal with 50% duty, look at sharth's answer. Your code above pretty clearly makes it look like you want a 200Hz clock enable, which is not the same, though probably actually better. Which is it? – fru1tbat May 16 '14 at 14:00

So this code generates a 200 Hz clock based on a 100 Mhz clock.

We note that: 100 MHz / 500000 = 200 Hz

So, we need to take our 100 Mhz clock, and every 500000 cycles, we would have a full cycle of the 200 Hz clock that we would like to generate. Since we want the high time and low time to be the same, we know that we should oscillate the new clock every 500000 / 2 cycles.

From the perspective of the code, we will use hexadecimal, so it's worth noting that 500000 / 2 == 0x3D090.

architecture foo of blah is
signal clk_200Hz : std_logic := '0';
signal counter : unsigned(19 downto 0) := x"00000";
begin

clkdiv : process (clk_100Mhz)
begin
if rising_edge(clk_100Mhz) then
if counter = x"00000" then
counter <= X"3D090"
clk_200Hz <= not clk_200Hz;
else
counter <= counter - 1;
end if;
end if;
end process clkdiv;

end architecture;

• Why rising_edge(clk) is preffered? Because our professor was pissed off when I didnt use clk'event and clk = '1' and why X"3D090" ? Is this an 200Hz clock divider? – Anarkie May 14 '14 at 9:30
• As to rising_edge: stackoverflow.com/questions/15205202/clkevent-vs-rising-edge/…. 3D090 is half of 7A120. We want the clock to invert every 400 Hz, which makes a rising_edge every 200 Hz. This code makes a (poorly named) clock EN that functions at 200 Hz. – Bill Lynch May 14 '14 at 13:16
• @sharth - you may want to explain why you've made some of these changes. – fru1tbat May 16 '14 at 13:13
• @sharth so 200 Hz rising edge and then 200 Hz falling edge, together makes 400 Hz? Did I understand correct, that is why we are dividing with 2? – Anarkie May 16 '14 at 21:01
• You are convoluting your units a bit. Waiting 250,000 counts per transition gives you twice that delay for a full cycle, which gives you the inverse in frequency, i.e. half. – fru1tbat May 17 '14 at 11:28