I have 100Mhz system clock and I would like to have a 200Hz Enable signal for enabling the state machine. I need a clock divider for this process and thought about this :
clkdiv : process (clk) begin if (clk'event and clk = '1') then -- rising clock edge -- default value EN <= '0'; clkcntr <= clkcntr - 1; if clkcntr = 0 then clkcntr <= X"7A120"; -- 500000 decimal value EN <= '1'; end if; end if; end process clkdiv;
I have seen other implementations on the internet they always start first dividing with 100Mhz to 2. In my case I should decrement 250000 time to match this, is this because clk is 1-0-1-0-1-0-1-0, since we are interested on the rising edge we should also consider the falling edge times? I would be glad if someone can demonstate a proper clock divider. Then when I am done I would like to go into the state machine with an if condition
if EN = '1' then go into the state machine end if;
In the end I would like the duration of my output signal from the FSM be 200Hz long, would this be correct? Are there other ways for implementing this?