Verilog Assignment

Question

I'm designing a Fahrenheit to Celsius converter using algorithmic state machines. I'm trying to get the following code to run, but all I get for output is 0.

module FtoC(clk, F_input, C_output);
input clk;
input [8:0]F_input;

output [6:0]C_output;
reg [6:0] C_output = 0;

reg [1:0] state =0;
reg [8:0] A, R;


always @ (posedge clk)
case (state)
0: begin state <= 1; C_output <= 0; A <= F_input; R <= 0; end
1: begin state <=2; R <= ({(A - 32), 2'b00} + A); end
2: if (R>9) begin R <= R - 9; C_output <= C_output + 1; end  

       // else state <= 0;

endcase

endmodule

Answer 1

First of all, you need to include your testbench, since it is just as important as your design, especially when things are not working as expected.

Secondly, the R <= ({(A - 32), 2'b00} + A); line is wrong. Like alex.forencich already pointed out, you want (A-32)*5 = 5A-160, but are actually doing (A-32)*4+A = 5A-128, which is not the same.

Instead, R <= ({A, 2'b00} + A) - 160; should work.

For simple simulations, you can use the online simulator edaplayground.com.

Here's a snapshot of your code (using edaplayground) with the correction and a testbench, showing the correct output value of C = 37 when the input is F = 100:

Answer 2

Check your testbench. I got it to run, save for a couple of minor issues. First, iverilog choked on {(A-32),2'b00} as (A-32) does not have a definite width. You can use a temporary variable to fix this issue. Second, I presume you are trying to do (A-32)*5, but instead you are doing (A-32)*4+A, which ends up giving you the wrong result. I corrected both of these issues by adding a temporary reg t and using t = (A - 32); R <= ({t, 2'b00} + t); . I tested with F_input = 100 and got the expected result of C_output == 37, after quite a few clock cycles.