Do any flip-flops use separate clock levels for "sample" and "propagate" events

Question

Many kinds of sequential logic require that the output of one register be fed into the input of another register which is strobed by the same clock. In such logic, it's necessary to ensure that a changed output from the first register cannot affect the input of the second until after the hold time of the second register has been satisfied. If data flows in one direction, it may be possible to delay the clock of the downstream device, but if data needs to flow bidirectionally it may be difficult to ensure that all devices have sampled their data before any changes can percolate to any device's data input; getting reliable behavior from high-speed logic devices would require sharp clock edges even when using very slow data rates.

It would seem that in many cases this problem could be eased considerably if flip flops' clock inputs defined two distinct levels with non-overlapping tolerance bands: a "sample" level (perhaps 15%-30% VDD) and a "propagate" level (e.g. 45%-60% vdd), such that setup time would be required before the clock signal reaches 15% VDD, hold time would be measured after it reaches 30% VDD, minimum propagation would be measured after it reaches 45%, and maximum propagation after it reaches 60%.

Such specifications would ensure that provided every device sees the clock signal reach 30% of VDD before any device sees it reach 50% of VDD, then setup/hold times would automatically be met for any devices with a zero hold time; positive hold times could be met by limiting the rate of rising clock edges.

It would seem that this approach should allow system designers great flexibility in balancing clock edge speed with clock rate requirements, and would allow much better noise immunity than Schmitt trigger inputs (unless all registers are clocked by the output of the same Schmitt trigger, they may switch at different times, and even when using one Schmitt trigger, logic may get sunk if a fuzzy clock signal makes the output go metastable). Are there any logic families that use such behavior to improve the performance and reliability of their edge-triggered logic functions?

Answer 1

I dunno what the modern chips do internally, but for instance the 8080 used a non-verlapping two-phase clock:

I think the problem with your approach is

• the levels at which CMOS logic is active is not easily controlled, and/or controlling it accurately would put extra demands on other aspects (geometry, size, yield, etc.)

• there is not realy a level at which a FF samples the signal, rather there is a level 1 at which the first (master?) latch stops sampling, and a level 2 at which the second (slave?) latch starts sampling the master's output. When level 1 << level 2 (wide band between them) and the clock edge is not too steep you automatically have a 'deadband' as you want.