Operating a MOSFET as a switch: A strange dip occurs on the drain voltage

Question

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I'm trying to debug a circuit shown in Fig. 1.

The gate of the FET is driven with a square wave 0...3 volts. The voltage source V1 = 3.3V. The circuit is built to control the voltage presented to the non-inverting input of an operational amplifier. R2 and R3 are trimmers, so the two input voltages can be trimmed to different values if needed.

Driving the FET with a square wave I notice a rather odd behaviour. The voltage between R1 and R2 are shown in Fig. 2 as a function of time (green). The voltage of Vgs is drawn blue.

As can be seen, the voltage v+ first dips to a negative value and then rises slowly to the steady state value. When the voltage v+ should drop to the lower value (vgs = 3 V) it first overshoots after going down to the steady state. The simulation and oscilloscope measurements agree together.

What could be causing this, and how can i get the voltage between R1 and R2 (green waveform) to be as closes as a square wave as possible. Fet in use is Si2318CDS. Datasheet provided in the comment. I have tried higher Vgs amplitudes han 3V.

Answer 1

There is capacitance from the gate to the drain. Normally (as in a power switch) this is more of a concern for the gate drive (especially when the drain voltage is changing a lot and fighting the gate drive), but the capacitance also couples changes in the gate voltage to the drain.

In this case you have 270mV on the drain when it is off, and ~0mV when it is on and the gate drive is more than 10x higher (3V).

There are a variety of techniques to reduce this- a smaller MOSFET will help because it has less capacitance, but you will pay in terms of Rds(on). Another approach is to balance off the injected charge by another transistor driven with something like the opposite waveform. You can find multiple patents describing these techniques.

Good commercial analog switches can have charge injection in the 1pJ range, which sounds low, but it's actually still a problem in some cases.

Edit: From your waveforms you can see two time constants. From the MOSFET datasheet, page 3, "Capacitance" shows the output and reverse transfer capacitances vs. Vds. They increase sharply for low (or, by extrapolation) slightly negative Vds. For large negative Vds the body diode will start to conduct significantly so these waveforms will not scale- if you increase the drive voltage to 10V you will see a change in the shape.

You might want to look at this answer from Andy and (upvote if it is helpful, of course).

Answer 2

This is the drain-gate capacitance. It's a simple R-C circuit coupling the gate voltage (square wave) into the drain circuit.

Considering the impedances, use the smallest (lowest C) MOSFET you can find. (There's a reason small signal JFETs are often used for switching low level signals)

A more detailed analysis needs the MOSFET datasheet and the time axis scale factor (or frequency of the square wave).