CMOS logic gate output

Question

What happens to Voh and Ioh when the number of loads connected to the output of this logic gate increases?

My interpretation is: the increase in number of loads decreases the equivalent impedance, which causes the current Ioh to increase. Is this view correct? But I can't visualize what happens to Voh.

^{simulate this circuit – Schematic created using CircuitLab}

Answer 1

Inside the inverter there is a switch, this switch flips between Voh and Vol. Now, this switch has resistance (like pretty much everything) and so when you pull more current, the switch isn't able to pull the output as close to Vcc or GND as it would have been able to other wise. Basically, Voh drops and Vol rises (assuming equal loads in both directions)

Answer 2

The voltage divider created by the totem pole output and the loads causes V_OH to drop below V_DD. If this voltage drops below V_IH before the current reaches I_OH then the digital circuit may glitch. If I_OH is reached before V_IH then the totem pole output may be damaged. Neither is a good outcome which is why one or more buffers may be needed if the load count is excessive.