How do I observe a PLL's frequency tracking once the lock has been acquired?

Question

I am trying to design a basic PLL (second order-type 1) to understand its dynamics. I am using Cadence Virtuoso for simulations. I have designed a voltage controlled oscillator that has a center frequency (at Vcontrol = VDD/2) of 16MHz, an XOR phase detector and a passive RC low pass filter.

As I've observed, for an input signal of 15-20MHz, the loop acquires the lock.

I want to observe how the PLL tracks any change in the input frequency, once the lock has been acquired. Is there any way I could simulate this?

Parametric analysis provides different set of curves for different input frequencies. This does not tell you much about the response of loop. If I could observe, once the loop is locked, how the output frequency tracks the input say for a step change in input frequency.

Answer 1

how the output frequency tracks the input say for a step change in input frequency

If you look at the control voltage into the VCO, its average value (ignoring ripple) is representative of the output frequency produced: -

If this filtered control voltage is stable (not end stopped) then the PLL is in equilibrium or has settled to a constant steady state error (ignoring noise).

So, if you made a step change to the reference frequency, you would see the classic 2nd order response of the control voltage: -

Picture taken from here

But, because there are many, many types of loop filters and amplifiers you could get variations rather like you would with a PID controller: -

Picture taken from here

In other words, with a simple proportional control (kp), there will be a frequency lock error because the loop gain is finite. If the gain were made too high then it could become unstable. So, the integral term becomes useful (ki) and this can reduce the frequency error to zero without necessarily causing instability. The differential term (kd) can act as a "brake" on the control loop and significantly reduce overshoot.

I'm stating all this because it is not 100% clear what your control loop actually is.

Answer 2

The best way to do this would be to simulate with a step change in frequency. If your circuit simulation tool does not have frequency generator sources that can step their frequency then you have to design this into your circuit. One way is to have two frequency generators at two different frequencies that are gated through a 2->1 MUX. The MUX select control is your timed step change signal.

Some tools permit parametric control of certain parameters of the signal source. If you have that then you can connect the two frequency generators at two different frequencies in series and parametically change the amplitude of the first from VPP to 0 and the second from 0 to VPP. The parameter can be the step change control level.

Answer 3

PLL's with XOR gate mixers have many characteristics.

1) capture ratio vs Loop BW and Capture time vs loop BW - the former defines the ratio of the fo / Delta f which is related to Q of a BPF but is nonlinear since SNR affects the Pull-in or capture range.

2) The Overshoot and dampening factor are directly and inversely related in any 2nd order system.

3) Generally a 2nd order PLL is improved by changing the pump filter or integrator using phase lag-lead compensation with a series R added to C and then shunting that with C/10.. This also improves "Phase or gain margin" of the loop and controls overshoot directly with slight jitter increase at 2f clock.

4) Another approach is to slowly reduce the loop gain of the integrator to reduce the BW and jitter of the clock while it still locked. Since jitter of clock compounds timing margin by adding to inter-symbol interference (ISI) jitter, minimizing this is a compromise between capture time and jitter, unless you have an adaptive loop gain design.

note above spread in f1,f2 is normally 5:1 to 10:1 ratio for lead-lag RC loop compensation to reduce ringing significantly.

Answer 4

If you have already a VCO model (within the PLL) why not using a similar model to tune the input frequency using a linear voltage ramp as a control signal?