Single Activation Falling Edge Detector

Question

What's the best way to design a single activation falling edge detector?

I have a 3.3V power supply, and a separate GPIO signal that will begin toggling after power is applied. I need a signal to permanently toggle after the first falling edge, and then it should never toggle again no matter what the input does. This should be asynchronous and only depend on the input signal (or derivatives or maybe an inverted copy of the input signal).

^{simulate this circuit – Schematic created using CircuitLab}

One thought I've had is to use a negative edge triggered DFF, with my INPUT signal as the DFF's CLK input, and PWR as the DFF DATA input. Then when INPUT toggles low, output toggles. The problem is next time the input toggles low, the output will change again, and I only want it to happen one time.

Any thoughts on how to accomplish this will be appreciated.

Answer 1

If using a flop, please check the power-on state of its output is well determined, which might need a special reset circuit.

Myself, I'd use this:

• PNP+NPN wired as thyristor
• PNP base acts as trigger
• Trigger is capacitive-coupled to your toggling GPIO.

Power-up behavior is known: a thyristor wakes up open.

Slow voltage changes (ie, stuff that happens at supply ramp-up) does not pass through the capacitor, which should be small enough to only trigger the circuit on a fast edge from the GPIO pin.

Just my 2c.

Answer 2

The output of a d-type flip flop wont change unless PWR has changed. I guess you are thinking of a j-k flip flop which toogles its output with a clock edge

Answer 3

Causing a low to high transistion from the first falling edge is easy. There are various ways to do this with a flip-flop. For example, a negative edge triggered D flip-flip with input high and initially cleared (output low) will do it.

Triggering on the falling edge is easy. Probably the more complicated issue is when to reset this device, unless you want it to output high forever after. Having a reset input needs to be taken into account up front.

Answer 4

If you are familiar with finite state machines(fsm), a 2-state-moore-fsm would do your work. You can use pwr as input, input as clock(your dff should be falling edge), output as output. The transition from the first state to the second should only occur when pwr is 1 by the first state. By the second state, the state shouldn't change no matter what value pwr has.

But if you are using a master clock in your system, i wouldn't actually recommend input line to be used as clock. Then you should use input as the second input and use the master clock as clock. But in this case your fsm will probably contain more than two states.