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I am new to Quartus, and have been trying to test out my 32-bit ALU on Quartus 13.1. When I try the functional simulation, I get a string of Zs. The results for the individual components, like the fullAdder, display the results fine. What can I do to view the result(inout) in a hex representation?

Edit: There was an issue with the Quartus 13.1 edition. It works perfectly fine on the 16.1 edition.

  • \$\begingroup\$ My crystal ball is not supporting schematics/HDL view. \$\endgroup\$ – Eugene Sh. Feb 1 '18 at 16:13
  • 1
    \$\begingroup\$ The Zs mean high impedance, so a bit is probably disconnected somewhere. \$\endgroup\$ – Samuel Feb 1 '18 at 16:47

Without posting your HDL code, it's difficult to determine what exactly is the problem. However, something outputting Zs in simulation likely indicates that the output hasn't been assigned. For instance, when simulating this module:

module simple(input a,b, output o);
    wire o_internal;
    assign o_internal = a^b;
endmodule // simple

o has the value Z. So you probably want to go over your ALU and make sure that you are actually assigning to your output signal.


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