Initialising FPGA internal RAM from file

Question

I have a design that relies heavily on internal dual port RAM found in the FPGA and I want to take advantage of the fact that blockram can have power-on initial values to populate all this memory with random data. How I plan to do this is to make a named pipe through a pre-synthesis TCL script, pump random data into it and have it read by a VHDL function. I've seen similar things done, only with text files.

My question is, doing it this way, will all instances of the blockram module be filled with the same pseudo-random data, or will each be synthesised "separatedly" somehow, ending up with different pseudo-random data, which is what I'm after?

The tools are Vivado 2015.4 and the part is Zynq-7000 (7-series Xillinx FPGA), by the way

EDIT/clarification:

I've seen people reading block ram initial content from a text file in VHDL and the result is synthesisable. I want to do something similar, but rather than a plain text file, I'm thinking of using a named pipe with the write end connected to a bash script to generate random initial blockram content in the bitstream. However, I'm not sure exactly what the synthesis tool does with the block ram module: is each instance of the same VHDL design file synthesised in one pass, making the RAM content of all repeated instances identical, or are they treated separately, thus populating them with different random data?

Answer 1

I'm still not fully understanding your question, so I'm answering what I think you want. What you can do is read a different file for each ram. You do that by constructing the file name dynamically.

Example: in 0.txt

0101
1010

in 1.txt

0110
1001

the VHDL(-2008):

library ieee;
package array_types is
    use ieee.std_logic_1164.all;
    type slv_array is array (natural range <>) of std_logic_vector;
end package;

use work.array_types.slv_array;

entity ram is
    generic(ram_init : slv_array);
end entity;

architecture rtl of ram is
    subtype ram_data_type is slv_array(0 to ram_init'length-1)(ram_init(0)'length-1 downto 0);
    signal ram_data : ram_data_type := ram_init;
begin
end architecture;

entity init_ram is end entity;

library ieee;
architecture rtl of init_ram is
    constant ram_width : positive := 4;
    constant ram_depth : positive := 2;
    use work.array_types.slv_array;
    subtype ram_data_type is slv_array(0 to ram_depth-1)(ram_width-1 downto 0);
    
    use std.textio.all;
    use ieee.std_logic_1164.all;
    impure function load_file(index:natural) return ram_data_type is
        constant file_name : string := integer'image(index)&".txt";
        file file_pointer : text;
        variable line_data : line;
        variable line_value : bit_vector(ram_width-1 downto 0);
        variable ram_data : ram_data_type;
    begin
        file_open(file_pointer, file_name, read_mode);
        for line_index in 0 to ram_depth-1 loop
            readline(file_pointer, line_data);
            read(line_data, line_value);
            ram_data(line_index) := to_stdlogicvector(line_value);
        end loop;
        file_close(file_pointer);
        return ram_data;
    end function;
begin
    gen_rams: for i in 0 to 1 generate
        inst_ram: entity work.ram
            generic map(
                ram_init => load_file(i));
    end generate;
end architecture;

Result:

edit

of course you could also create the random value inside vhdl.