I am new to VHDL, and I'm working with an off-the-shelf UART block. I'm trying to create a test bench and override the data width, but I get errors saying that my signals are undeclared:

ERROR - C:/Users/xxx/Documents/VHDL/Digikey UART/tb_uart.vhd(41,24-41,32) (VHDL-1241) clk_freq is not declared

ERROR - C:/Users/xxx/Documents/VHDL/Digikey UART/tb_uart.vhd(42,24-42,33) (VHDL-1241) baud_rate is not declared

ERROR - C:/Users/xxx/Documents/VHDL/Digikey UART/tb_uart.vhd(43,24-43,31) (VHDL-1241) os_rate is not declared


I have gone over many examples and am not sure what is wrong with my code, but I suspect it's a syntax issue.

I won't flesh out my test bench until I get a better handle on my issue. I am using Lattice Diamond 3.10.

library ieee;
use ieee.std_logic_1164.all;

-- entity declaration
entity tb_uart is
end tb_uart;

-- architecture declaration
architecture bhv of tb_uart is
    -- instantiate uart block
    component uart 
        generic (
            clk_freq   : integer    := 50_000_000;
            baud_rate   : integer   := 19_200;
            os_rate     : integer   := 16; -- oversampling rate
            d_width     : integer   := 18; -- bits sent/received
            parity      : integer   := 1;
            parity_eo   : std_logic := '0' -- '0' for even, '1' for odd
        port (
            clk     : in std_logic;
            reset_n : in std_logic;
            tx_ena  : in std_logic;
            tx_data : in std_logic_vector(d_width-1 downto 0);
            rx      : in std_logic;
            rx_busy : out std_logic;
            rx_error: out std_logic;
            rx_data : out std_logic_vector(d_width-1 downto 0);
            tx_busy : out std_logic;
            tx      : out std_logic
    end component;

    -- signals & constants
    signal tx_to_rx : std_logic;
    constant  clk_per : time := 1_000_000_000 / clk_freq;        


    u1: uart
    generic map (
        clk_freq    => clk_freq,
        baud_rate   => baud_rate,
        os_rate     => os_rate,
        d_width     => d_width,
        parity      => parity,
        parity_eo   => parity_eo
    port map (
        clk     => clk,
        reset_n => reset_n,
        tx_ena  => tx_ena,
        tx_data => tx_data,
        rx      => rx,
        rx_busy => rx_busy,
        rx_error => rx_error,
        rx_data => rx_data,
        tx_busy => tx_busy,
        tx      => tx


        clk <= '0';
        wait for ( clk_per ns);
        clk <= '1';
        wait for ( clk_per ns);
    end process;

 end bhv;

1 Answer 1


In your generic map, you've mapped the formal parameter clk_freq to a local symbol of the same name, yet this local symbol does not exist in your testbench.

You should either map it to a specific value, or if you want to use the default value, you should not map it at all.

  • \$\begingroup\$ Thanks. Do I do this inside the generic map? \$\endgroup\$
    – Bort
    Sep 28, 2018 at 15:55
  • \$\begingroup\$ Better question -- Why use a generic map at all, if I can my set my override values in the component generic section? I'm not clear on the purpose of the generic map. \$\endgroup\$
    – Bort
    Sep 28, 2018 at 15:58
  • 2
    \$\begingroup\$ Exactly! You would use the generic map when you have more than one instance of the component that need different values. \$\endgroup\$
    – Dave Tweed
    Sep 28, 2018 at 16:22

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