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I need to do a lab that seemed like it was simple, but for some reason i cant get the right output for this function. its G(0)= T1T3'+T5T7'. These are data inputs.. I can only use NAND and NOR gates. The set up i have now is as shown belowenter image description here

I continue to get a constant low output for G(0). I would really appreciate it if someone could let me know where the schematic is wrong. Thanks in advance!

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  • \$\begingroup\$ You're asked that \$G_0=T_1\overline{T_3}+T_5\overline{T_7}\$ ... However, you have \$G_0=\overline{\overline{T_1\overline{T_3}}+\overline{T_5\overline{T_7}}}\$ \$\endgroup\$ – KingDuken Oct 15 '18 at 2:37
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Try making the final NOR gate, whose output is G(0), into a NAND, since this is a sum of products expression. If you use DeMorgan's law, you'll then see that you have two AND gates feeding into an OR, which is your original expression.

schematic

simulate this circuit – Schematic created using CircuitLab

The inverters can be NOR or NAND, as both perform the same inverter function here.

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