module A (input a, input b)
...
module B (input a, input b)
...
endmodule
endmodule
Is the above allowed in Verilog?
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2\$\begingroup\$ It looks like nested modules are only allowed in SystemVerilog svref.renerta.com/sv00027.htm , asic-world.com/systemverilog/hierarchy3.html \$\endgroup\$– Eugene Sh.Commented Apr 26, 2019 at 15:02
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2 Answers
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I do not think it is allowed, may be if you want to do, you should use System Verilog. More information is available in this link.
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Nested module declarations are only allowed in SystemVerilog. The nested module is only visible for instanciation within the module is contained.
If you are looking to have two different module definitions with the same name, it's possible to do this in Verilog with libraries and the config construct.
