Doubt about Phase Locked Loop

Question

1. How is it possible that the Signal Output will have the same frequencies as the Reference Signal?
   \$f_1\$, Frequency of the Reference Signal;\$f_2\$, Frequency of the VCO.
   1. Let's assume that \$f_1>f_2\$, so the phase detector will create a positive voltage \$V_1\$
   2. At this point \$V_1\$ will ensure that the VCO will increase his frequency of oscillation.
   3. At this point \$f_1=f_2\$, and this will make \$V_1=0\$, but if \$V_1=0\$, then \$f_2\$ will drop.
   4. If \$f_2\$ drops, \$f_1\$ will become again \$>f_2\$, and \$V_1\$ will be positive.

In according to this reasoning this circuit will create an oscillation, where am I wrong, (Since this circuit will create a very stable Signal Output with the same frequency of the Reference)?

2. Why this circuit need an error in the phase for create a lock and so Phase1 must be not equal to Phase2?
3. What will happen if \$f_2>f_1\$, will the Phase Detector create a Negative Voltage?

Answer 1

Simplistically, the loop filter can contain an integrating element, so that the output of the phase detector going to zero doesn't necessarily mean the control voltage of the VCO will be zero.

To make things more complex, remember that phase is the integral of frequency, so by using a phase detector rather than a frequency detector, you've already included an integrating device in your control loop. The loop filter will likely need to include both integrating and differentiating components to keep the loop stable, while also allowing the loop to react quickly to disturbances in the VCO behavior, thus minimizing phase noise of the output.

Answer 2

my first 'pll' was like this

^{simulate this circuit – Schematic created using CircuitLab}

To get a lock, I had to vary the input "Fref". I then noted a varying input duty cycle would change the delays between input edges (Fref edges) and the astable-oscillator edges.

Within a few years I was deep into non -EXOR PFDs at 20MHz (for data recovery in telemetry) and 2-pole-1-zero loop filters, with variable Icharge_pump to allow adjusting the loop bandwidth as SNR and Jitter varied. Because our task was data-recovery, the timing error budgets were low nanoseconds; we used ECL in the PFD (phase frequency detector) and 2GHz diffpairs in the charge pumps --- your national defence $ at work.