# Doubt about Phase Locked Loop

1. How is it possible that the Signal Output will have the same frequencies as the Reference Signal?
$$\f_1\$$, Frequency of the Reference Signal;$$\f_2\$$, Frequency of the VCO.
1. Let's assume that $$\f_1>f_2\$$, so the phase detector will create a positive voltage $$\V_1\$$
2. At this point $$\V_1\$$ will ensure that the VCO will increase his frequency of oscillation.
3. At this point $$\f_1=f_2\$$, and this will make $$\V_1=0\$$, but if $$\V_1=0\$$, then $$\f_2\$$ will drop.
4. If $$\f_2\$$ drops, $$\f_1\$$ will become again $$\>f_2\$$, and $$\V_1\$$ will be positive.

In according to this reasoning this circuit will create an oscillation, where am I wrong, (Since this circuit will create a very stable Signal Output with the same frequency of the Reference)?

1. Why this circuit need an error in the phase for create a lock and so Phase1 must be not equal to Phase2?
2. What will happen if $$\f_2>f_1\$$, will the Phase Detector create a Negative Voltage?
• the error voltage is not DC .... moodle.insa-toulouse.fr/pluginfile.php/2665/mod_resource/… – jsotola Jun 1 '19 at 21:01
• as @jsotola said, the phase detector detects phase, not frequency. Phase is a linear function of frequency difference. – Marcus Müller Jun 1 '19 at 22:20
• Your concern is well-founded, but is a common issue. Almost ANY feedback loop contains the seeds of oscillation - it is up to the designer to avoid it. In your case, the loop filter must be designed properly. If it is underdamped, any change in open-loop VCO characteristic may produce unstable operation, usually only temporary. – WhatRoughBeast Jun 2 '19 at 0:14
• Which frequency is $f_1$ and which is $f_2$? Your block diagram doesn't say which is which. Also, what's $V_1$? – The Photon Jun 2 '19 at 2:13