I have a basic question regarding PLLs and how they actually achieve lock.
I was told that the PLLs go into the lock when the output of a phase detector is zero, therefore to drive VCO an integrator is used between the phase detector and the VCO to keep the voltage at a constant level.
However, I am struggling to understand how exactly the integrator keeps that voltage on a constant level.
If the input of an integrator drops to zero then its output over time will also drop to zero as it is an integral of input, no? I even ran Multisim simulations with an integrator to understand its behaviour better. When I was applied a sine wave to it that would mimic characteristics of an analogue multiplier phase detector, every time I turned off the voltage on the rising edge when phase difference = pi/2, the integrator's output would drop to zero after a few seconds.