I am writing some basic verilog code that blinks an LED at some frequency. The code for the design file is the following:
`timescale 1ns/1ns
module FPGA_Testing(input reset, input clk, output reg LED);
reg [32:0] counter;
reg state;
always @ (posedge clk) begin
if(reset == 1) begin
counter <= 0;
state <= 0;
end
else begin
counter <= counter + 1;
state <= counter[20];
end
end
always @* begin
LED = state;
end
endmodule
and the test module is here:
`timescale 1ns/1ns
module FPGA_Testing_tb;
reg clk;
wire LED;
reg reset;
FPGA_Testing test(
reset,
clk,
LED
);
initial
begin
clk = 0;
reset = 1;
#10
reset = 0;
end
always
begin
#5 clk = !clk;
end
endmodule
When I compile the code, I get these as my warnings and critical warnings:
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Critical Warning (169085): No exact pin location assignment(s) for 3 pins of 3 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning: Warning: File FPGA_Testing_run_msim_rtl_verilog.do already exists - backing up current file as FPGA_Testing_run_msim_rtl_verilog.do.bak11
Warning: Warning: File FPGA_Testing_run_msim_gate_verilog.do already exists - backing up current file as FPGA_Testing_run_msim_gate_verilog.do.bak11
And then when I run a RTL simulation with ModelSim, I get this
As you can see, the clk and reset values in the testbench file are correct, but the clk and reset values in the design module are both Hi-Z(which I suspect is the reason why I get undefined behavior from the other values in my design module). I am pretty sure I did the connections correctly, so I am unsure as to why I get these Hi-Z values.
