With the 74LS164 8 bit parallel out serial shift registers, I'm confused about a few things. In the datasheet (page3) on the logic diagram why do they suggest using an active low inverter before the active low pin on the clear line? Is this for some sort of buffer?

My second question is if this is a 8-bit register why on the clear-shift-clear timing diagram (page 2) do they have 11 clock pulses? Would we be limited to 8 clock pulses before the registers are full and 11 clock pulses result in potential loss of data?

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    \$\begingroup\$ They don't suggest anything of the sort. Are you sure you linked the correct data sheet because I can't see the timing diagram you mentioned either? \$\endgroup\$
    – Andy aka
    Dec 9, 2019 at 16:26
  • \$\begingroup\$ Everything on page 3 is inside the chip, not something you add \$\endgroup\$ Dec 9, 2019 at 16:56
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    \$\begingroup\$ @ScottSeidman, thanks, I don't know why I thought it was external. Is there a general purpose for the using that type inverter before an active low on the clear? Isn't the signal just being inverted back to the original? So 1->0->0? \$\endgroup\$
    – pnd1987
    Dec 9, 2019 at 18:30
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    \$\begingroup\$ It's normally just for buffering purposes, so the clear and clock input pins present a single TTL load instead of (in this case) 8 loads in parallel. \$\endgroup\$
    – Finbarr
    Dec 9, 2019 at 19:17

1 Answer 1


The logic diagram shows the internal logic circuit of the device - inside the chip.

Once the underlying logic circuit is known, practically any question on the device logic state behaviour can be answered. And in conjunction with full device voltage and timing specifications, practically all questions on the device behaviour and operation can then be answered.

That's the ideal case. In reality, not all datasheets are of good enough quality. Here, it's a matter of opinion but I've found the various 74xxyy datasheets to be pretty comprehensive most of the time.

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The 'Typical clear-shift-clear sequences' diagram (page 2) shows exactly that. It's not a 'Single 8-bit serial-parallel transfer' diagram.

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The shift register in this device can shift in any number of bits. All but the most recent 8 bits will appear on the parallel outputs. The rest would have tipped off the end of Qh.

It's not uncommon to daisy-chain the devices to produce more than 8 parallel outputs, with the Qh output of one device connected to the A or B input of the next device. Some bits would pass through earlier devices on their way to later devices and the diagram makes it clear how each device would behave in that situation.

So there's more for that diagram to show than just a single byte transfer.


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