VHDL test bench for input port assignment

Question

I am trying to depict port 3 of microcontroller which acts a I/O and as special functions like timers interrupts in VHDL.

The code is as follows:

    library IEEE;
    use IEEE.std_logic_1164.all;
    entity testIO is 
    port (
    p3: inout std_logic;
    op:out std_logic;
    r0:in std_logic;
    sel_line:in std_logic;
    T0:out std_logic;
    Clk    :  in std_logic;
    ip:in std_logic
    );
    end testIO;
    architecture beh of testIO is
    Begin
    process(clk)
    begin
    if Clk'event and Clk='1'then
    if r0 = '1' then
    T0 <= p3;
    else
    p3 <= 'Z';
    end if;             
    if sel_line = '1' and r0 = '0' then
    p3 <= ip;
    else
    p3 <= 'Z';
    end if; 
    if sel_line = '0' and r0 = '0' then
    op<= p3 ;
    else
    p3 <= 'Z';
    end if; 
    end if;
    end process;
    end beh;

My testbench is as follows:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    entity testIO_tb is
    end testIO_tb;
    architecture Behavioral_tb of testIO_tb is
    component testIO is
    port (
    p3: inout std_logic;
    op:out std_logic;
    r0:in std_logic;
    sel_line:in std_logic;
    T0:out std_logic;
    Clk    :  in std_logic;
    ip:in std_logic
    );
    end component;
    signal p3_s,sel_line_s,T0_s,ip_s,op_s: std_logic;
    signal r0_s:std_logic:='1';
    signal Clk_s:std_logic:='0';
    begin
    DUT1:testIO port map(
    p3   => p3_s,
    op   => op_s,
    r0   => r0_s,
    sel_line => sel_line_s,
    T0   => T0_s,
    Clk   => Clk_s,
    ip   => ip_s
    );
    Clk_s <= not Clk_s after 5ns;
    process
    begin
    if r0_s='1' then
    p3_s<='1';
    else
    p3_s<='Z';
    end if;
    wait for 10ns;
    r0_s<='0';
    sel_line_s<='1';
    ip_s<='0';
    p3_s<='Z';
    wait for 10ns;
    sel_line_s<='0';
    wait for 10ns;      
    end process;
    end Behavioral_tb;

In the simulation,the value of p3 is not set to '1' at 0ns though I am setting it to 1 in testbench. It is setting to 1 at 5ns. I am not sure why.

Also T0 value is not getting updated at 5ns and ip value is not copied to p3 at 15ns.

Answer 1

To your question why p3 is not set at 0ns: Your process in testIO is assigning values at the rising_edge of clk. What do you have at 0ns? No rising edge. So it's undefined what p3 is at the beginning. Look up some vhdl samples and have a look for reset behaviour.

If you look at testIO:

1. You check if r0 = '1' => T0 <= p3
2. You check if sel_line = '1' and r0 = '0' => p3 <= ip else p3 <= 'Z'
3. You check if sel_line = '0' and r0 = '0' => op <= p3 else p3 <= 'Z'

You see what happens here? You assign p3 in multiple paths at the same time. Look at your compiler messages.

So... I would recommend you, to make a truth table and create your logic based on this. You can assign your p3 with one if elsif else statement and not with multiple if else statements to prevent missbehaviour.