How to build large demultiplexers using SystemVerilog?

Question

Note: This question about demultiplexers is similar to but not identical to this question which is about multiplexers.

I want to build a fully parameterisable demultiplexer in SystemVerilog. So far, I know how to build demultiplexers of variable widths like this:

module scale_mux #(parameter WIDTH = 1) (
  input logic sel_a,
        logic [WIDTH-1:0] in,
  output logic [WIDTH-1:0] out_a, out_b);

  always_comb
    unique case (sel_a)
      1'b1 : out_a = in;
      1'b0 : out_b = in;
    default: out = 1'bx;
    endcase

endmodule 

I also know how to extend this for 1:4 and 1:8 demultiplexers. But the number of case statements for large demultiplexers will be a lot.

I'd like to build a demultiplexer in which the number of inputs is variable. I'm not sure how I can extend the case statement for the n input case, do you have any ideas?

Answer 1

module generic_demux #(parameter WIDTH = 1, 
                       parameter NUMBER = 2, 
                       localparam SELECT_W = $clog2(NUMBER)) 
 (input logic [SELECT_W-1:0] sel, 
  input logic [WIDTH-1:0] mux_in,                   
  output logic [WIDTH-1:0] out [NUMBER-1:0]);
  
  assign out[sel] = mux_in;
    
endmodule  

I used part select to select the right output to which the input has to be routed. The select line width is logarithm to the base 2 of the number of inputs. The select line width should be declared as localparam so that it won't be overridden.