How to build large multiplexers using SystemVerilog?

Question

Note: This question about multiplexers is similar to but not identical to this question which is about demultiplexers.

I want to build a fully parameterisable multiplexer in SystemVerilog. So far, I know how to build multiplexers of variable widths like this:

module scale_mux #(parameter WIDTH = 1) (
  input logic sel_a,
        logic [WIDTH-1:0] in_a,
                    in_b,
  output logic [WIDTH-1:0] out);

  always_comb
    unique case (sel_a)
      1'b1 : out = in_a;
      1'b0 : out = in_b;
    default: out = 1'bx;
    endcase

endmodule

I also know how to extend this for 4:1 and 8:1 multiplexers. But the number of case statements for large multiplexers will be a lot.

I'd like to build a multiplexer in which the number of inputs is variable. I'm not sure how I can extend this case statement for the n input case, do you have any ideas?

Answer 1

module generic_mux #(parameter WIDTH = 1, 
                     parameter NUMBER = 2, 
                     localparam SELECT_W = $clog2(NUMBER)) 
 (input logic [SELECT_W-1:0] sel, 
  input logic [WIDTH-1:0] mux_in [NUMBER-1:0],                   
  output logic [WIDTH-1:0] out);
  
  assign out = mux_in[sel];
    
endmodule    

I used part select to select the input and route it to the output. The select line width is logarithm to the base 2 of the number of inputs. The select line width should be declared as localparam so that it won't be overridden.