In SystemVerilog, is the set of operators usable in a continuous assignment smaller than that usable in an always statement?

Question

My question is, essentially, as stated in the title. For what it's worth, it's prompted by a comment made by Stuart Sutherland on page 256 of his RTL Modelling with SystemVerilog:

The primary RTL modeling construct for combinational logic is the always proce­dure, using either the general purpose always keyword or the RTL-specific always_comb keyword. These always procedures can take advantage of the robust set of operators programming statements that are discussed in Chapters 5 and 6, whereas continuous assignments are limited to using only SystemVerilog operators.

I have bolded the relevant sentence. The suggestion seems to be that there are more operators which can be used while in an always statement but, even after flipping back through the book, I can't seem to find any suggestion of this.

Chapter 5 is titled "RTL Expression Operators" and Chapter 6 "RTL Programming Statements". I suspect Sutherland was using "operator" very inclusively to also mean things like if-else statements, case statements, etc., in which case the claim makes sense.

Answer 1

I do not have access to the book, but I agree with your suspicion that the author was not solely speaking about SystemVerilog operators (like = & <<), but meant other constructs as well, such as if/else and case statements.

From a recommended coding practice point of view, continuous assignments are great if the logic is pretty simple:

assign a = (b & c) | (d & e);

But, as the logic gets a lot more complex, lines of code can get very long, which means they will be harder to read, understand and maintain.

In that case, it is better to use procedural assignments (always blocks). A common use of an always block is for the combinational logic for the next-state logic of a finite state machine. While it might be possible to use a complex continuous assignment, it is much more natural to use a case statement.

Answer 2

The correct answer to the question in title is yes, there are some operators you cannot use in continuous assignment (or any non-procedural context); specifically the inc_or_dec_expressions (++/--) or operators_assigment (+=/>>=,etc)

For example

bit a,b,c;
assign a = b + c--;

The SystemVerilog BNF syntax prevents some of these expressions, but there should be some text somewhere disallowing side-effects in non-procedural contexts.